SIRIPURAM SAI KIRAN

Seeking a challenging role in a dynamic semiconductor organization for a long career, where I can apply my knowledge and experience to contribute for the development and success of the organization. As a continuous learner, I actively seek to improve my knowledge on other domains of ASIC flow aiming to deepen my understanding of designs and further augment my professional capabilities to explore new frontiers in chip designing.

• Strong Experience in Block Level Physical Design Implementation
• Experience in setup of Backend flow for 5nm, 16nm
• Experience in developing scripts for Automation
• Hands on Multiple EDA tools of Cadence, Synopsys, MentorGraphics.
• Experience in solving challenges related to Congestion, Timing such as Density screens, Cellpadding, Useful skew, Ostrich Correlation and ECOs.
• Handled Multiple blocks in 5nm and 16nm SOC projects.
• Knowledge on ILMs, Hierarchical Flow.

• Received Star performer Award in Ceremorphic Technologies Pvt Ltd towards my contribution to the company.
• Received Appreciation Award towards my work on successful completion of Tape out on 5nm
• 3-star coder in Python in HackerRank
• Secured admission into IIT Roorkee in M.tech in VLSI for Industry professionals.
• Organized Technical Symposium at CVR College of Engineering
• LinkedIn badges in python basic and Linux

Innovus,  Quantus, PrimeTime,  Calibre, Formality, Voltus

DC-compiler,star-RC

PSS(Processor sub system)(16nm)

Responsibilities: Netlist to GDSII

Floorplan to Routing

RC-Extraction, STA, Physical verification(DRC,LVS)

IR/EM

LEC

Macros: 170

Instance count: 3Million

Freq: 1.5GHz

Processor_sub_system2(5nm)

Responsibilities: Netlist to GDSII

Floorplan to Routing

RC-Extraction, STA, Physical verification(DRC,LVS)

IR/EM

LEC

Macros: 120

Instance count: 1Million

Freq: 1GHz

mxu_top (16nm)

Responsibilities: Netlist to GDSII

Floorplan to Routing

RC-Extraction, STA, Physical verification(DRC,LVS)

IR/EM

LEC

Macros: 16

Instance count: 1Million

Freq: 1.5GHz

compute_system(16nm)

Responsibilities: Netlist to GDSII

Floorplan to Routing

RC-Extraction, STA, Physical verification(DRC,LVS)

IR/EM

LEC

Macros: 16

Instance count: 0.5 Million

Freq: 1.5GHz

Aonss(5nm)

Responsibilities: Netlist to GDSII

Floorplan to Routing

RC-Extraction, STA, Physical verification(DRC,LVS)

IR/EM

LEC

Instance count: 50k 

Freq: 100MHz

UART Transmitter(28nm)

Responsibilities:Floorplan to Routing

Macros: 40

Instance count: 50K

Freq: 413MHz