Nirmal Varghese

Seeking a position as Physical Design Engineer with an opportunity that will allow me to further develop my skills, while sharing my expertise, and contributing to the success of the organization.

• English (R/W/S)
• Malayalam (R/W/S)
• Hindi (R/W/S)
• Tamil (S)

• Date of Birth: 09/30/97
• Gender: Male
• Nationality: Indian
• Marital Status: Married

1. BRECK

Client : AMD

Technology Node : 6nm

Tools : Fusion Compiler, Prime Time

Frequency : 1 GHz

Duration : 12 months

Roles & Responsibilities

• Handled 3 medium complexity partitions with ~0.6 M gate count.
• Created multiple scripts for feedthrough buffering for controlled routing and buffering of the feedthrough nets.
• Helped flow team to enable secondary grid creation through the flow.

2. GTCHE D2G XE3 X2

Client : INTEL

Technology Node : 5nm

Tools : Fusion Compiler, Prime Time

Frequency : 3 GHz

Duration : 4 months

Roles & Responsibilities

• Handled 2 high complexity partitions with 4 M gate count.
• Unit bounding, path grouping and repeater planning done for proper routability and timing convergence.
• Floorplan level issues were highlighted for better convergence of section timing.

3. GTCHE D2G XE3 X3

Client : INTEL

Technology Node : 5nm

Tools : Fusion Compiler, Prime Time

Frequency : 3 GHz

Duration : 10 months

Roles & Responsibilities

• Handled 2 partition with high complexity with 4M gate count from PNR to ECO, and handled one more block in addition to this during ECO stage.
• Supported in the convergence of several other partitions.
• Converged timing and routability through methods like unit bounding, path grouping, RP planning, clock push-pull, manual routing, VSS chopping etc.
• Implemented multiple timing, DRV, RV, LV fixes as ECOs scripts.
• Successful tape out in fast pace environment within deadline.

4. Hutchins Creek Test Chip

Client : INTEL

Technology Node : 7nm

Tools : Fusion Compiler

Duration : 8 months

Roles & Responsibilities

• Handled PNR , LV, RV for one partition .
• Hands on experience on Layout verification.
• Worked on Cheetah2 flow

5. IO96

Client : INTEL

Technology Node : 10nm

Tools : Fusion Compiler

Duration : 6 months

Roles & Responsibilities

• Supported a partition with medium criticality.