Summary
Overview
Work History
Education
Skills
Accomplishments
Extracurricular activities
Timeline
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Azmira Mounika

Physical Design Engineer
Hyderabad

Summary

Passionate physical design engineer at intel with 8 years 3 months experience in synthesis/PNR/Pv/signoff/STA for high frequency designs in Core & SoC.

Worked on multiple functional blocks in 14nm/10nm/7nm technology core processors with DC,ICC/ICC2/FC,STA (primetime) Synopsys,caliber signoff tools for high-speed designs.

Have supported standard library team with library release builds for the projects with technology 10nm/14nm/7nm – includes collaterals build like layout,schematic,characterization and other second level collaterals generation and installation.

Have worked on multiple SoC partitions in Display, Media subsystems in 18A node with Cadence genus innovus tools. Implemented end to end Physical Design implementation flow from RTL to GDS, synthesis, place, CTS, route and signoff flows with Cadence genus innovus tool.

Overview

8
8
years of professional experience
6
6
years of post-secondary education

Work History

SoC Design Engineer

Intel corporation
07.2022 - 07.2025
  • Have owned couple of partitions from display and media subsystems in 18A node
  • Had implementation end to end partition physical design flow implementation using cadence genus innovus tools
  • Worked on macro placements according to the logic cells placement, floorplanning , pnr, solved many CTS related issues, by reducing skew and improving latency for overall timing and clock network quality improvements
  • Executed many late stage functional and manual ECO’s with high accuracy and reduced turnaround time, ensuring timely sign off and without impacting project timelines
  • Contributed to successful project tapeout by performing and closing all sign off checks including static timing analysis, extraction, layout verification, IR Drop, logic equivalence checks and thoroughly analysing and resolving all associated errors/warnings to ensure clean sign off.

Physical Design Engineer

Intel corporation
06.2018 - 07.2022
  • Have owned multiple timing/area/power critical functional blocks of processor core as a PDE
  • RTL to GDS flow – Synthesis , floor planning , placement , CTS , route and signoff using synopsys DC/ICC/ICC2
  • STA – timing convergence over multiple corners at high frequency upto 4.5ghz on latch and flop based designs
  • Physical verification – DRC , LVS , clean up and sign off
  • Reliability verification – EM , SH , IR Drop , noise signal integrity using intel tools, quality fixes based on silicon feedback
  • Formal equivalence verification of blocks against RTL
  • Power convergence on high frequency design upto 4.5 ghz
  • Post silicon speed paths fixes – timing closure on speed paths in post si design in 14nm nodes
  • Have supported standard library team with library release builds for the projects with technology 10nm/14nm/7nm – includes collaterals build like layout , schematic , characterization and other second level collaterals generation and installation.
  • Have worked on various library project releases to design with quality checks performed.

Project Standard Library Member

Intel bangalore
06.2018 - 01.2019
  • I have worked on various project standard library releases and delivered to the design, include collaterals views generation and installation. quality checks, timing characterization, PPA checks.

Digital design intern

06.2017 - 06.2018
  • Worked on various functional block design in processor core – STA/DC/ICC/ICC2/FEV
  • Design ,FEV,STA, LVS, Noise analysis ,Reliability verification

Education

M.tech - VLSI SD

National Institute of Technology Warangal
Warangal
01.2016 - 01.2018

B.tech - Electronics and communication

Keshav Memorial Institute of Technology
Narayanaguda, Hyderabad
01.2011 - 01.2015

Skills

RTL2GDS flow, Synthesis (Design Compiler), DFT/Scan Insertion, Floorplanning, P&R (ICC2/Fusion Compiler) ,Clock Tree Synthesis , Route ,

DRC/LVS/ERC/ANTENNA (Caliber) ,Static timing Analysis (Prime time), Functional & timing ECO Implementation ,Reliability checks ,LEC ,PPA optimization ,TCL scripting,

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Accomplishments

  • Received Team level award for high quality in time library paranoia checks done before tape-in on the standard library for project design.
  • Received Cluster level recognition on converging multiple designs with high quality delivery of the design.
  • Written a poster on optimization of rentention cell placement in SoC Display partition, which was recognized by the upper management during the innovation Tech day.

Extracurricular activities

sketching

Timeline

SoC Design Engineer

Intel corporation
07.2022 - 07.2025

Physical Design Engineer

Intel corporation
06.2018 - 07.2022

Project Standard Library Member

Intel bangalore
06.2018 - 01.2019

Digital design intern

06.2017 - 06.2018

M.tech - VLSI SD

National Institute of Technology Warangal
01.2016 - 01.2018

B.tech - Electronics and communication

Keshav Memorial Institute of Technology
01.2011 - 01.2015

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Azmira MounikaPhysical Design Engineer