Kakumanu Abhigna
Bangalore
Summary
To build a career in VLSI domain, pursue challenging and engaging opportunities with progressive organizations that allow me to improve my skillsets and contribute effectively towards personal and organizational growth.
Overview
1
1
year of professional experience
1
1
Certification
Work History
Synthesis Engineer
MediaTek
11.2022 - Current
- Perform Physical aware Synthesis of Block to generate a netlist with clean timing, high Clock gating, high MBFF ratio, congestion-free and low leakage.
- Perform Logic Equivalence Check (LEC) on RTL to Netlist, netlist to netlist and few other quality checks like TVSDC, CTS-Sanity and Electric Rule Check (ERC).
- Perform Low power checks using Cadence Conformal tool (CLP).
- Working closely with Front end, Physical design and DFT teams for better QoR and to meet timing requirements.
Graduate Trainee Engineer(Physical Design Trainee)
RV-VLSI
04.2022 - 10.2022
Block level implementation of Lakshya sub-system, a design with 40nm Technology, performed Floorplan, Power Plan, Placement, CTS, Routing, and STA on 40nm block.
Experience in IC Compiler II - Synopsys and Synopsys PrimeTime.
Education
B.Tech. - Electronics And Communication Engineering
G. Narayanamma Institute of Technology And Science
Hyderabad, Telangana, India2019
12th - Mathematics, Physics, Chemistry
Narayana Junior College
Nellore, Andhra Pradesh, India2015
SSLC
Ratnam Concept School
Nellore, Andhra Pradesh, India2013
Skills
- Comprehensive knowledge of Synthesis flow and experience in Physical aware synthesis
- Good understanding of Cadence CONFORMAL for LEC and CLP, knowledge of various quality checks like ERC, CTSSANITY, TVSDC, etc
- Hands-on experience in Industry standard tools like Fusion Compiler, IC Compiler II - Synopsys, PrimeTime – Synopsys
- Good understanding of Digital Electronics, Verilog basics, Linux basics, understanding and modification of TCL scripts
- Comprehensive knowledge of ASIC Flow and in-depth understanding of APR Flow involving Floorplanning, Powerplanning, Placement, Clock Tree Synthesis, and Routing
- Basic understanding of Static Timing Analysis, generating and analyzing timing reports of various paths, fixing setup and hold violations
Accomplishments
• Established ‘MINDSPARK’, a technical club in GNITS, and served as Joint Secretary.
• First prize in Technical Paper Presentation on 'Hyperloop’ organized by IEEE, GNITS.
Certification
1. RV PROJECT - BLOCK LEVEL IMPLEMENTATION OF LAKSHYA SUBSYSTEM- Performed Floorplan, Powerplan, Placement, CTS, Routing, and STA on 40nm block.
2. Internship at ACCENTURE TECHNOLOGY in SAP-IS Oil & Gas under the project titled ‘My Concerto’
3· Project in High-Speed VLSI Architecture for Advanced Encryption Standard Algorithm.
4. Internship experience at BSNL, Nellore in communication topics in OCB exchange.
Timeline
Synthesis Engineer
MediaTek
11.2022 - Current
Graduate Trainee Engineer(Physical Design Trainee)
RV-VLSI
04.2022 - 10.2022
B.Tech. - Electronics And Communication Engineering
G. Narayanamma Institute of Technology And Science
12th - Mathematics, Physics, Chemistry
Narayana Junior College
SSLC
Ratnam Concept School
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