Gaurav Dhiman

Project 1: Advanced Micro Devices (AMD) Inc.

• Design: Medusa(OLR)
• Process: TSMC 7 nm
• Tool: Fusion Compiler, Formality.

Role and responsibilities:

• 16 Tiles ownership, Performed Synthesis using industry-standard tools (Synopsys Fusion Compiler), optimizing for timing, area, and power across multiple PVT corners.
• Executed Static Timing Analysis (STA) using tools like PrimeTime, analyzing setup/hold violations and ensuring timing closure for high-performance designs.
• Worked on Logical Equivalence Check (LEC) to verify RTL vs synthesized netlists consistency, ensuring functional correctness post-synthesis.
• Debugged and resolved timing violations (setup/hold, transition, capacitance) through constraint refinement, buffering, and logic restructuring.
• Validated SDC constraints , including clock definitions, false paths, multicycle paths, and I/O delays.
• Implemented and analyzed clock gating strategies to enhance power efficiency while maintaining timing integrity.
• Collaborated with RTL, DFT, and Physical Design teams to achieve timing closure and resolve cross-functional issues.
• Analyzed timing reports (TNS/WNS) and implemented fixes to improve overall design performance and robustness.
• Checks for area, MBB ratio, CG ratio, etc., comparison with previous milestones, and debug for degradations, if any.

Project 2: Advanced Micro Devices (AMD) Inc.

• Design: Pacifica NOC-Tiles.
• Process: TSMC 7 nm
• Tool: Fusion Compiler, Formality.

Role and responsibilities:

• Performed RTL-to-gate synthesis up to initial optimization (init-opt) stage, delivering timing- and area-optimized netlistss for downstream PnR.
• Executed pre-layout and post-layout STA , analyzing setup/hold, SI, and cross-corner timing to ensure robust timing closure across MMMC scenarios.
• Utilized DMSA (Distributed Multi-Scenario Analysis) for concurrent multi-corner, multi-mode timing analysis and generated ECOs to fix timing violations.
• Collaborated with PnR teams by providing timing-driven ECO recommendations and validating post-route timing convergence.
• Maintained SDC constraints , including clocks, generated clocks, false paths, and multi-cycle paths for accurate timing signoff.
• Optimized multibit register inference to improve area, reduce clock power, and manage routing congestion.
• Debugged and resolved timing/DRV violations (setup/hold, max transition, max capacitance, clk xtalk, noise etc.) using buffering, resizing, clk pushing, etc. techniques.
• Executed Equivalence using Formality, LP checks using Conformal Low Power tools as a part of final signoff checklist.
• Established strong working relationships with clients through exceptional communication skills, fostering trust and collaboration.
• Achieved successful project outcomes by maintaining accurate documentation and meeting strict deadlines.

Project 1: Intel Technologies Pvt. Ltd.

• Design: LilyCreek(LLK)
• Process: 1276.5
• Tool: Fusion Compiler, Conformal EC, VC Static

Role and Responsibilities:

• Full Multi voltage Partition ownership where we need to meet all the requirements like floorplanning, voltage area, Placement, CTS, Routing.
• Need to work on all sign-offs, including FEV, VCLP, Caliber, LV, STA, xor2spec, etc.
• Ownership of FEV and VCLP for all 17 partitions and Fullchip.
• Have done STA checks and implemented timing ECOs to close the design to desired quality.

Project 2: Intel Technologies Pvt. Ltd.

• Design: D2G_1(Display 2 Graphics).
• Technology: TSMC - 5nm
• Tool: Fusion Compiler, Conformal Equivalence Checker.

Role and Responsibilities:

• Handled FEV for almost 35 pars and almost 30 reused pars.
• Several FEV checks like F18, xbuf, stdcell, ctech etc.
• Ownership of FEV for partitions of 4 Sections/Super sections.
• Worked on setting up the ECO flow for Front-End team enabling them to implement functional ECOs for bug fixes.
• Addition of Constraints and Mappings in FEV for spine/ribs implementation done by spine team for CTS where clock port additions for resolving clock issues/better timing

Project 3: Intel Technologies Pvt. Ltd.

• Design: Newsport Springs2(NTS2)
• Process: 1278.3 -18A
• Tool: Fusion Compiler, LEC, VCLP

Role and Responsibilities:

• Ownership of FEV & RapidESD for 18 partition and Fullchip FEV/VCLP.
• Several FEV checks like F18, Seq-Merging, RTL rule checks, Top metal layers edits etc.
• Fixing Not-mapped, Non-Equivalences, Aborts, Sequential Const Failures etc.
• Addition of Constraints and Mappings for Top Level connectivity checks done thorough FEV.

Project 1: Benchmarking and Validation

• Designs: Imagination (IMG Rascal), Avago Doppler, etc.
• Technology: 7 nm, 5 nm
• Tool: Genus Synthesis Solution, by Cadence.

Role and Responsibilities:

• Check for Slack (WNS & TNS), area, power, with respect to previous builds, and find the responsible integration to newer builds that caused the degradations.
• Responsible for validating nightly builds on a daily basis.

Current GPA: 8.14 CGPA

GPA: 75.1%

GPA: 65.3%