B.C. RAHUL

To be a key driver of growth, organizational and personal, while constantly updating myself to meet the industry needs and ensure maximum competitiveness with ethical efficiency.

A technology driven professional with 5.2 year’s of experience in DFT. Currently working as DFT Engineer in LeadSOC Technologies since July 2019 with hands-on experience in DFT implementation.

• NetApp Certified Data ONTAP 8.07-Mode Administrator (NSO-154)
• Cisco Certified Network Associate (CCNA)

• Project 1, Fastscan, Xcelium, Spyglass, LEC, 7nm, RAMBUS, Bengaluru, Karnataka, Ran Spyglass on the design RTL and generated DFT scan ready reports., Inserted BSCAN at the RTL level using Tessent shell., Used Fastscan for ATPG generation for Stuck-at and Transition fault models., Ran both Zero-delay and Timing simulations for the patterns generated.
• Project 2, Testkompress, Xcelium, Primetime, 28nm, Western Digital, Bengaluru, Karnataka, Setting-up environment for MBIST simulations., Generating block level patterns and retargeting them at the top level.
• Project 3, Design Compiler, Testkompress, VCS, 28nm, NXP Semiconductors, Bengaluru, Karnataka, Done scan insertion at the block level using Design Compiler., Done ATPG using Tessent TestKompress.
• Project 4, Genus, Testkompress, Xcelium, 28nm, NXP Semiconductors, Bengaluru, Karnataka, Done scan insertion at the block level using Genus., Done ATPG using Tessent TestKompress.
• Project 5, Genus, Fusion Compiler, Testkompress, 7nm, Google, Bengaluru, Karnataka, Done scan insertion at the block level using Genus., Done ATPG using Tessent TestKompress.

• Date of Birth: 08/18/87
• Gender: Male
• Nationality: Indian

• English
• Hindi
• Telugu

• Worked on Spyglass and generated DFT scan ready reports.
• Experience in Scan Insertion and Scan DRC’s.
• ATPG pattern generation for Stuck-at and Transition fault models.
• Simulating ATPG patterns and validation.
• Experience in Post silicon debug activities.
• Experience in Boundary scan, JTAG TAP Controller implementation using Tessent shell.
• Experience in Memory BIST simulations.
• Basic knowledge of P1500 core wrapper technology.
• Knowledge in Verilog coding and PERL scripting.