Suraj Singh
Uttar Pradesh
Summary
I am working in Insemi as a DFT Engineer .I have hand on experience in Scan, ATPG and Simulations on Synopsys tools,I had also worked as a Physical Verification Intern in Synopsys ,I worked there in backend team in DRC(design rule check).I had done my M.tech in VLSI design from NIT Jalandhar.I am passionate about learning new technologies and soving challenges problems in field of VLSI.
I am looking for full time opportunity and open to all for any role.
Overview
2
2
years of professional experience
Work History
DFT Engineer
Insemi technology Pvt Ltd
Bangalore, Karnataka
05.2024 - Current
- Worked on smaller designs which were part of SOC and perform scan ,ATPG and no-timing simulations and analyze their log files & output reports.
- Learn the basics of DFT concepts and faults classification
- Learn scan insertion flow using synopsys dc tool
- Solve the various DRC violations
- Learn ATPG flow using synopsys tetramax tool
- Knowledge of OCC , EDT and JTAG/IEEE 1149.1
Graduate Technical Intern
Synopsys India Pvt Ltd
Noida, UP
08.2022 - 08.2023
- Worked on Physical verification check i.e DRC(Design Rule Checks) using ICV tool
- Done handcoding of the DRC runsets against the drm provided by foundries and parse it whether syntax correct or not
- Created the testcases against each rule to validate the DRC rule
- Validate the DRC runset of various foundries against its testcases and classify them into passed and failed category
- Debug the failed cases by tracingback and finding its root cause and correct them and rerun those testcases untill DRC are clean
- Also draw the layouts of some basic circuits on Custom Compiler and made them DRC clean
Education
M.tech - VLSI Design
NIT Jalandhar
Jalandhar, Punjab,India09-2023
B.Tech - Electronics Engineering
REC Kannauj
Kannauj, UP,India09-2020
Skills
Digital Electronics
Verilog
Tcl,bash
ASIC Design Flow
Physical Design & verification
Static Timing Analysis
DFT
Linux
Adaptability
Time Management
Tools Used
Design Compiler(DC)
Tetramax
Custom Compiler
ICV
Xilinx ISE 14.7
Silvaco TCAD
Certifications & Awards
Python for Everybody Coursera.
VSD - Physical Design Flow - Udemy.
VSD - Static Timing Analysis -Part1 - Udemy.
VSD - Static Timing Analysis -Part2 - Udemy.
Secured 95 percentile in GATE 2021.
Timeline
DFT Engineer
Insemi technology Pvt Ltd
05.2024 - Current
Graduate Technical Intern
Synopsys India Pvt Ltd
08.2022 - 08.2023
M.tech - VLSI Design
NIT Jalandhar
B.Tech - Electronics Engineering
REC Kannauj