Summary
Overview
Work History
Education
Skills
Timeline
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Pranjal Giri

DFT Design Engineer

Summary

Accomplished Senior DFT Engineer at Texas Instruments with expertise in ATPG analysis and low-power DFT implementation with a proven track record in enhancing test coverage and reducing test time through innovative solutions.

Overview

7
7
years of professional experience

Work History

Senior DFT Engineer

Texas Instrumetns
07.2019 - Current
  • Led DFT implementation and verification on a 210k FF design, implementing MBIST, ATPG, custom BSCAN, and pattern delivery for silicon bring-up
  • Owned ATPG coverage analysis and pattern generation for multiple SoCs, implementing additional hooks to boost test coverage.
  • Verification of DFT testmodes including ATPG, MBIST, NVM tests(EFUSE), security and device life cycle states in unit-delay, timing annotated and power-aware simulations
  • Created timing constraints for test modes and collaborated with the STA team to close timing across test modes, including scan, MBIST, and JTAG
  • Supported silicon bring-up, yield analysis, and debug of test failures on ATE
  • Performed RTL DFT checks,DFTLint checks using JasperGold, and IP ATPG for multiple SoCs
  • Defined and verified DFT overrides and test hooks for analog components in mixed-signal SoCs for RF, BLE, and PMU components
  • Co-authored a granted US patent tailored towards test time reduction
  • Supported PE team in implementing firmware fixes in post-silicon through the ARM AP interface with hard-coded patterns to reduce test time.
  • Collaborated with multiple cross-functional teams across RnD sites in different time-zones to deliver quality design deliverables
  • Working on an ML project to predict IR drop for screening scan patterns

Physical Design Intern

Texas Instruments
05.2018 - 07.2018
  • Worked with the Physical Design team to create a simplified Visual Basic-based application to show a GUI-based image of SoC floorplan including the IO layout
  • Created a Python-based script for verifying the ROM content coded within the LAFF file (pre-GDS equivalent), which extracted the embedded bit code in the ROM image

Education

Bachelor of Technology - Electrical Engineering

Indian Institute of Technology, Kanpur
Kanpur, India
04.2001 -

Skills

Scan Insertion and Compression

ATPG Analysis and Fault simulation (Stuck-at, TDF, IDDQ, SDD, Bridging, Cell-aware)

Memory BIST(MBIST), Logic BIST(LBIST)

Custom Boundary Scan (JTAG 11491)

Core DFT achitecture design including security, boot configurations and device life cycle states

DFT verifications in simulation (RTL, unit-delay, Timing annotated and power-aware)

Silicon Debug, Test-time reduction and yield improvement

Scripting (TCL, Python, Perl)

Tools: Cadence Modus, JasperGold, Genus, Xcelium, Vmanager

Timeline

Senior DFT Engineer

Texas Instrumetns
07.2019 - Current

Physical Design Intern

Texas Instruments
05.2018 - 07.2018

Bachelor of Technology - Electrical Engineering

Indian Institute of Technology, Kanpur
04.2001 -

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Pranjal GiriDFT Design Engineer