VISHNU R

Client : Broadcom

Project #1 :
Technology : 5nm
Tools Used : Mentor (Tessent) tools, Synopsys (dve, Verdi) tools.
Languages used : Perl and Tcl.
Role and Responsibilities:

• Handled 4 blocks and did DFT design insertion (SCAN/EDT/MBIST)
• ATPG Pattern generation & retargeting.
• LEC verification.
• Fixing DRC and Meeting coverage goals.
• Simulation failure debug at block/chip level (timing/notiming).

Project #2:

Technology : 3nm

Tools Used : Mentor (Tessent) tools, Synopsys (dve, Verdi) tools.

Languages used : Perl and Tcl.

Role and Responsibilities:

• Handled 4 blocks and did DFT design insertion (SCAN/EDT/MBIST)
• ATPG Pattern generation & retargeting.
• LEC verification.
• Fixing DRC and Meeting coverage goals.
• Simulation failure debug at block/chip level (timing/notiming).

Projects : ADL-N, MTL-D, STL, ACR-T_NOC
Tools Used : VCS, Venus
Role and Responsibilities:

• Responsible for DFx functional validation of PLL, DTS - RTL and GLS simulation.
• Responsible for MBP Validation.
• Toggle coverage analysis for different cores using Venus and preparing exclusion list.
• For ACR project done the functional verification for 8 instances of APB and also done the test plan and test case generation for the same.

Client : Qualcomm
Technology : 7nm
Tools Used : TetraMax, VCS
Role and Responsibilities:

• Core level pattern generation (DRC fixing and reaching targeted coverage) and top level porting for 7 cores (2 sub-systems)
• Core level, Sub-system level and SOC level simulations for both timing and ZD.
• Creating debug patterns if failures come at silicon testing.

Client : Broadcom
Technology : 7nm
Tools Used : Mentor (Tessent) tools, Synopsys (dve, Verdi) tools.
Languages used : Perl and Tcl.
Role and Responsibilities:

• Handled 4 blocks and 2 top level groups and did DFT design insertion (SCAN/EDT/MBIST).
• ATPG Pattern generation & retargeting.
• Formal verification.
• Fixing DRC and Meeting coverage goals.
• Simulation failure debug at block/chip level (timing/notiming).