SANTHOSH REDDY MULA
Summary
I would like to work for an organization which provides me the opportunity to work in a challenging environment where I can utilize my technical abilities and improve my skills and knowledge along with the growth of the organization.
Overview
4
4
years of professional experience
4
4
years of post-secondary education
Work History
Senior DFT Engineer
Quest Global
01.2025 - Current
DFT Engineer
L&T Technology Services
04.2021 - 01.2025
- Hands on experience of latest DFT tools from Mentor Graphics, Synopsys
- Worked on complex and multi-million gate design with hierarchical architecture
- Experience in Test coverage improvement with different techniques
- Experience in ATPG with fault models - Path Delay, SAF, TR
- Experience on Test vector generation for these models
- Test vectors simulation/validation with and without timing
- Experience in debugging simulation using Synopsys VCS
- Retargeted partition level patterns to tester level patterns using ICL, PDL and TCD and validated those to make sure the cut-points are valid
- Experience in generating and delivering the CA patterns to test the component level bugs
- Experience in post-silicon validation
- Worked on final production vector delivery
- Worked on diagnosing fail vector from tester
- Experience in Boundary scan pattern generation and Bscan Validation
Team Member
Intel
02.2024 - 08.2024
- Prepared ATPG Setup and ATPG DRC Cleanup
- ATPG Pattern Generation for stuck-at and at-speed Fault Models
- Technologies: VLSI, IP Level (Partition Level)
- Languages: Scripting
- Tools: Tessent Shell, VCS, Verdi
Team Member
Intel
08.2022 - 02.2024
- Understood DFT Specification for ATPG
- ATPG Pattern Generation for stuck-at and Transition Fault Models
- Doing Pattern Generation in the Block level and retargeting the same to the soc level
- ATPG Pattern Simulation with and without Timing
- Doing Gate level simulation using Synopsys VCS and Debugging simulation mis comparisons using VERDI
- Evil -X Pattern Generation and Simulation
- Critical Signal Checking
- Post Silicon Debugging
- Soc-level pattern generation and simulation
- Cleaned the clocking path from the source point for soc Simulations
- Technologies: VLSI, IP Level and SOC Level
- Languages: Scripting
- Tools: Tessent Shell, VCS, Verdi
Team Member
Intel
08.2021 - 08.2022
- Understood DFT Specification for ATPG
- ATPG Pattern generation for stuck-at and Transition Fault Models
- Doing Pattern Generation in Block level and retargeting the same to the soc level
- ATPG Pattern Simulation with and without Timing
- Doing Gate level simulation using Synopsys VCS and Debugging simulation mis comparisons using VERDI
- Resolving issues in both Timing and no-timing simulations
- Technologies: VLSI, IP Level and SOC Level
- Languages: Scripting
- Tools: Tessent Shell, VCS, Verdi
Team Member
Intel
01.2021 - 08.2021
- Understood DFT Specification for ATPG
- ATPG Pattern generation for stuck-at and Transition Fault Models
- Doing Pattern Generation in Block level and retargeting the same to the soc level
- ATPG Pattern Simulation with and without Timing
- Doing Gate level simulation using Synopsys VCS and Debugging simulation mis comparisons using VERDI
- Resolving issues in both Timing and no-timing simulations
- Doing Bscan Pattern Generation using Tessent TestKompress
- Boundary Scan Pattern generation and Validation by using various tests
- Technologies: VLSI, IP Level and SOC Level
- Languages: Scripting
- Tools: Tessent Shell, VCS, Verdi
Trainee and Intern
Maven Silicon VLSI Training Centre
10.2020 - 03.2021
Education
Bachelor of Electronics and Communication Engineering -
Mahatma Gandhi Institute of Technology
Ranga Reddy, Telangana 07.2015 - 05.2019
Skills
- C
- Verilog
- Simulation
- Static Timing Analysis(STA)
- ATPG
- ATPG DRC analysis and cleanup
- ATPG Pattern Validation
- stuck-at and transition Pattern Generation at block level
- Coverage analysis
- DFT Engineer with 4 years of experience in VLSI Industry
- Worked on ATPG and GLS in both IP level and SOC level
- Experience Working with Tessent Testkompress for ATPG and Coverage Improvement
- Experience on using Synopsys VCS Tool to do simulations (Timing and No Timing)
- Experience on working with Synopsys VERDI tool to debug simulations
- Technology Nodes: 5nm, 22nm
Work Summary
3+ Years of experience in DFT (Design for Test) Domain, Hands on experience of latest DFT tools from Mentor Graphics, Synopsys., Worked on complex and multi-million gate design with hierarchical architecture.
Timeline
Senior DFT Engineer
Quest Global
01.2025 - Current
Team Member
Intel
02.2024 - 08.2024
Team Member
Intel
08.2022 - 02.2024
Team Member
Intel
08.2021 - 08.2022
DFT Engineer
L&T Technology Services
04.2021 - 01.2025
Team Member
Intel
01.2021 - 08.2021
Trainee and Intern
Maven Silicon VLSI Training Centre
10.2020 - 03.2021
Bachelor of Electronics and Communication Engineering -
Mahatma Gandhi Institute of Technology
07.2015 - 05.2019
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