Abhishek Kulkarni
Bangalore
Summary
Proactive SOC Design Engineer in Texas Instruments , specializing in DFT integration and automation. Achieved high test coverage through innovative scripting and cross-functional collaboration. Proficient in Perl and Shell, Excel in enhancing DFT flows and resolving design challenges, driving efficiency and quality in SoC projects.
Worked on Industrial tools like Tessent TestKompress , SpyglassDFT, Verdi , Jasper , Cadence Genus.
Overview
6
6
years of professional experience
Work History
Senior DFT Engineer
Texas Instruments
Bangalore
07.2025 - Current
- DFT Integration of Sub-System for Automotive SoC Project.
- Worked with PD and RTL team to bring up Clocking for Sub-System.
- DFT RTL Lint Cleanup for Shift and Capture Modes using Jasper
- Worked on Scan-Insertion bring-up to target 100% on Scan Design.
SoC DFT Engineer
Intel Technology
Bangalore
07.2025 - Current
- Worked on DFT Integration of IP's, Partitions/Blocks for SoC and Subsystems.
- Involved in uArch planning and Implementation for TAPs, Memory BIST, SSN Network for multiple SoC Partitions and Subsystems.
- Performed Memory BIST Insertion with Memory repair and BAP Validation.
- Automated Memory Fuse calculations for Memory Repair flow using Perl Scripting.
- Handled UPF Issues by updating the design pre and post SD Feedback.
- Worked with Cross Functional Global Teams to define and implement DFT.
- Supported setting up DFT Integration flows for SoC Projects.
GRADUATE TECHNICAL INTERN
Intel Technology
07.2019 - 06.2020
- Worked on SoC Project by contributing to coverage analysis, ATPG pattern generation and Timing simulations.
- Responsible for creating ATPG Flow and cleaning up No-Timing Simulation setup issues.
- Test coverage improvement to meet the coverage of 99.5% for stuck at and 95% for AT-speed.
- Performed ATPG Pattern Generation, Coverage debug and GLS for Stuck-AT and AT-speed.
- Handled Various DFT DRC Violations for scan chain trace.
- Automated the DRC violations report in one excel for easier analysis.
- Simplified Coverage Debugging by implementing Automation using scripting.
Education
M.TECH - VLSI DESIGN
VELLORE INSTITUTE OF TECHNOLOGY
VELLORE06.2020
BE - ELECTRONCIS AND TELECOMMUNICATION
SMT. KASHIBAI NAVALE COLLEGE OF ENGINEERING
PUNE05.2016
Skills
- Perl
- Shell Scripting automation
- Cross-functional collaboration
- Simulation debug in Verdi
- Scan Methodology
- Memory BIST
Hobbies and Interests
- Playing Musical Instruments - Flute, Piano
- Travelling
- Playing Badminton, Table Tennis
Extracurricular Activities
Organized sports day at Intel. Arranged Quarterly GPTW Events.
Disclaimer
I hereby declare that the details furnished above are true and correct to the best of my knowledge and belief, I undertake to inform you of any changes therein, immediately.
Timeline
Senior DFT Engineer
Texas Instruments
07.2025 - Current
SoC DFT Engineer
Intel Technology
07.2025 - Current
GRADUATE TECHNICAL INTERN
Intel Technology
07.2019 - 06.2020
M.TECH - VLSI DESIGN
VELLORE INSTITUTE OF TECHNOLOGY
BE - ELECTRONCIS AND TELECOMMUNICATION
SMT. KASHIBAI NAVALE COLLEGE OF ENGINEERING
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