Ved Prakash
Bengaluru
Summary
Accomplished DFT Engineer from Ziotron Consulting Pvt. Ltd., adept in ATPG for block level and skilled in effective simulation debug techniques. Demonstrated expertise in enhancing ASIC flow processes and achieving significant VGR reduction. Known for meticulous attention to detail and a proactive approach to overcoming complex design challenges, ensuring project success.
Overview
3
3
years of professional experience
Work History
DFT Engineer
Ziotron Consulting Pvt. Ltd.
01.2021 - 04.2024
DFT Engineer | 04/2022 to 12/2023
Capgemini, Microchip- Bengaluru, India
ATPG for stuck at & at speed, handled broken scan chain issue, created a retarget environment for SOC, simulation for block level & debug mismatch for timing & no timing, worked on vector to gate ratio (VGR) reduction.
DFT Engineer | 08/2021 to 03/2022
UST, Intel, Malaysia
Handle 2 blocks in projects, Pattern generation for stuck at & at speed, Full chip pattern conversion for ATE tools.
Ziotron Consulting
DFT hand on tools training on Mentor tool |02/2021 to 7/2021
scan, EDT, ATPG for SAF & TDF, zero delay simulation
Education
M.Tech
Sarvepalli RadhaKrishnan University
Bhopal, India02.2018
B.Tech - Applied Electronics & Instrumentation
Sikkim Manipal Institute of Technology
Sikkim07.2015
Skills
ATPG for stuck at & at speed for block level
ATPG DRC's cleanup & coverage analysis
Simulation with timing & no timing
Simulation debug
TBIST insertion
Scan insertion & DRC cleanup
Vector Gate Ratio (VGR) reduction
Knowledge of EDT/Compression insertion
Clock structural knowledge for OCC
Knowledge in ASIC flow
EDA TOOLS
- Mentor Graphics: Tessent DFT Advisor, Tessent Fast scan, Tessent EDT, Questa simulator
- Cadence: Modus, NC Simulator
Timeline
DFT Engineer
Ziotron Consulting Pvt. Ltd.
01.2021 - 04.2024
M.Tech
Sarvepalli RadhaKrishnan University
B.Tech - Applied Electronics & Instrumentation
Sikkim Manipal Institute of Technology
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