CHAKRADHAR IPPILI

Worked in multiple clients during this tenure:

• Western Digital
• L&T
• Qualcomm
• Samsung (SSIR)

Leading a team of 8 people in my recent assignment

And was responsible for complete Scan deliverables

Worked on DFT for multiple ASIC's

Having vast exposure on EDA tools.

• Top level, Hierarchical scan insertion & pattern Generation
• Worked on compression techniques, to decide no of scan in & scan out ports required
• Worked on Low Power DFT Techniques
• Worked on Complex designs with a size of ~300Million Sequential instances
• Test point insertion to improve coverage & reduce pattern count using SpyGlassDFT
• Delivered the timing constraints to STA team for all modes of DFT
• Patten generation for blocks & Coverage analysis
• Re-targeting the patterns to TOP level using block level patterns in both SA TD modes using Tetramax
• ATPG pattern conversion (STIL to ATP) and pattern delivery
• Supported for tester on post silicon validation & Diagnosis for multiple projects
• Verified the HTOL sequence to be used for BURN-IN test
• Validated the preamble sequence for all DFT modes
• Performing Zero delay & Timing simulations from Blocks & Top
• Debugging the failures in both Zero delay & Timing Simulations
• Performing LEC between PRE DFT & POST DFT Netlists.

Worked for multiple clients during my tenure:

• Aura Semiconductors
• Sandisk/Western Digital
• Alliedvision

Had a great exposure to EDA Tools

Worked on complete Scan Insertion, ATPG & Simulations

• Hierarchal Scan insertion using DFT Compiler
• Test point insertion to improve coverage & reduce pattern count using SpyGlassDFT
• · Patten generation for blocks & Coverage analysis
• Stuck-at Pattern generation from Top in both (Intest & Extest Modes)
• Atspeed pattern generation from Top in both (Intest & Extest Modes)
• RAM-Sequential pattern generation for TOP
• Verified the HTOL sequence to be used for BURN-IN test
• Validated the preamble sequence for all DFT modes
• Performing Zero delay & Timing simulations from Blocks & Top
• Debugging the failures in both Zero delay & Timing Simulations
• Delivered the timing constraints to STA team for all modes of DFT
• Converting the ATPG patterns to ATE supportable format (ATP) & Pattern Delivery
• Worked on post silicon validation for complete scan patterns
• Worked on pattern diagnosis flow to debug post silicon failures
• MBIST implementation using SMS at block level
• Verified the MBIST inserted logic
• Test point insertion to improve coverage & reduce pattern count using SpyGlassDFT