Chit Khang Woo
Physical Design Timing Engineer
Butterworth
Summary
Accomplished Physical Design Timing Engineer with a proven track record at Intel, enhancing design quality and driving timing convergence activities. Expert in PrimeTime and adept at fostering a culture of continuous learning. Demonstrated success in improving timing constraints and achieving timing closure, showcasing both technical proficiency and mentorship capabilities. Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.
Overview
15
15
years of professional experience
Work History
Physical Design Timing Engineer
Intel
04.2021 - Current
- Physical design from RTL to GDSII except P&R: design quality check, synthesis, formal verification, constraints, timing analysis, signoff
- Drive FC/Subsystem/Partition timing convergence activities.
- Enhanced timing constraints SDC quality which including timing budget
- Collaborated with DFT engineer to improve DFT timing constraints
- Assisted P&R engineer in achieving timing closure for both partition and full-chip level
- Reviewed design inputs from stakeholders which including upf, sdc, & architecture specs
- Supported junior engineers through mentorship, offering guidance on complex problem-solving and technical skills development
- Facilitated knowledge sharing sessions on methodology, fostering culture of continuous learning among team members
Full-chip Timing Engineer
Intel
04.2017 - 04.2021
- Developed/executed FC timing analysis and timing modelling methodologies
- Collaborated with Frontend and Backend team on constraints development, timing closure/ signoff
Design Integration Engineer
Altera
06.2015 - 04.2017
- Developed clock integration IP (clock network), clock performance and reliability.
- Conducted spice simulation to validate clock performance
- Collaborated with P&R engineers to implement clock integration IP
- Managed correlation work on clock integration IP between Spice and PT
Analog Circuit Design Engineer
Renesas Semiconductor
04.2010 - 05.2015
- Involved in circuit design and improvemnet for low dropout linear voltage regulator, bandgap, oscillators, protection circuit and other analog circuitry
- Involved in LDO regulator design with different specification, experienced in accuracy and phase margin issues
- Performed QRC and post layout simulation, provided layout support by giving layout guidance for matching issue, DRC and LVS support
- Managed prototype evaluation and performed characterization to validate the circuit functionality
Pre-silicon Design Validation Engineer
Intel
06.2009 - 04.2010
- HS model build and test regression running
- Half system test debugging
- Developed scripts to enhance environment setup
Education
Bachelor of Science - Electronic Engineering
Universiti Malaysia Perlis (UniMAP)
Perlis 04.2001 -
Skills
PrimeTime
Design Complier (DC)
Fusion Complier (FC)
Conformal LEC
VCLP/UPF
SDC
DFT
Spice simulation
Timeline
Physical Design Timing Engineer
Intel
04.2021 - Current
Full-chip Timing Engineer
Intel
04.2017 - 04.2021
Design Integration Engineer
Altera
06.2015 - 04.2017
Analog Circuit Design Engineer
Renesas Semiconductor
04.2010 - 05.2015
Pre-silicon Design Validation Engineer
Intel
06.2009 - 04.2010
Bachelor of Science - Electronic Engineering
Universiti Malaysia Perlis (UniMAP)
04.2001 -
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