B. PAVAN

Results-oriented Electronics Engineer with expertise in Electronics and Communication, holding a Postgraduate Diploma in Microelectronics Systems and Devices from Newcastle University. Proficient in digital system design, Verilog/VHDL, and FPGA development, complemented by practical experience in embedded systems and FPGA-based projects. Committed to innovative problem-solving and enhancing engineering solutions through state-of-the-art hardware technologies.

• Program in C and data structures (Cranes Varsity)
• Advanced VLSI design and verification (Maven Silicon)

PNEUMONIA DETECTION USING DEEP LEARNING (B.E. Final Year Project)

• Processed a Kaggle chest X-ray dataset (~5,836 images) using Python, Keras, and TensorFlow, optimizing image pipelines suitable for embedded hardware acceleration and FPGA-based preprocessing.
• Implemented and benchmarked multiple CNN models (VGG16, ResNet50, InceptionV3, InceptionResNetV2, Xception) in Keras/TensorFlow, evaluating feasibility for embedded hardware and FPGA-based inference engines.
• Achieved ~88.9% classification accuracy with VGG16, highlighting potential for deploying optimized CNN inference cores in FPGA/embedded accelerators for real-time pneumonia detection.
• Developed a cross-platform GUI using PyQt5 and Qt, integrating CNN models for real-time predictions, adaptable to embedded displays and medical diagnostic devices.
• Utilized the Qt framework for cross-platform deployment, enabling portability to Linux boards, Raspberry Pi, and FPGA-based SoC platforms for embedded medical applications.

Design and analysis of a 16-bit RISC processor (M.S. Capstone Project)

• Designed and implemented a one-cycle 16-bit RISC processor datapath in Verilog, including instruction-fetch, decode, register file, ALU, and control modules, and synthesized it on a Xilinx Artix-7 FPGA using Xilinx Vivado.
• Engineered a modular ALU in Verilog with interchangeable 16-bit adder modules (Ripple-Carry Adder, Carry-Lookahead Adder, Carry-Select Adder), enabling plug-and-play substitution and comparative performance evaluation of each architecture.
• Implemented pipeline control units (program counter, branch/jump logic, hazard-detection) in Verilog, ensuring correct one-cycle execution of the custom RISC pipeline under conditional and iterative instruction flows.
• Conducted comprehensive synthesis and simulation in Xilinx Vivado, extracting resource utilization (LUT/FF counts) and critical-path timing (f_max) for each design; leveraged a UVM-based testbench to generate SAIF toggling activity and performed dynamic power analysis with Vivado XPower.
• Achieved key performance targets: the Carry-Lookahead Adder variant attained ~125 MHz (max clock), and the Carry-Select Adder achieved ~110 MHz (~25% speedup over the RCA baseline) on the Xilinx Artix-7 FPGA; documented trade-offs (~10% additional LUTs for CSA vs. RCA) to validate theoretical area–delay–power expectations.
• Provided hardware-validated guidance on adder trade-offs in FPGA-based RISC architectures: confirmed that the Ripple-Carry Adder minimized area/power, the Carry-Lookahead Adder maximized clock speed, and the Carry-Select Adder delivered a balanced performance compromise (~110 MHz with modest resource overhead).