BANAVATH VALYA
Bengaluru,KA
Summary
To acquire a position in an organization, where I can share my knowledge and innovative ideas among the team members and to become a successful employee in the organization I work for.
Overview
6
6
years of professional experience
Work History
Project Engineer
Bharat Electronics Limited (BEL)
Bengaluru, KA
04.2021 - Current
- Involved in Full product design life cycle and System integration with following duties and responsibilities: Preparing Electronics system architecture and coordinating with mechanical team for PCB Master drawing and chassis design
- Analyzing datasheets, Schematic design: Generating design file (.dsn), netlist and Bill of Materials (BOM)
- Analysis and review of PCB Layout files: Gerber file and board file (.brd)
- Assembly of PCBs: Components procurement and assembly of components
- Testing and troubleshooting PCBs: Physical inspection, continuity check, impedance measurement, current sense analysis for core voltages, voltage measurements at test points using Power supplies, reset and clock measurement using Digital Storage Oscilloscope
- RTL and System on Chip (SOC) design: Detection of FPGA using JTAG, VHDL coding, pin planning, system integration in Quartus system (Qsys), synthesis, timing analysis and finally System on Programmable chip (.Socfpga) file is generated
- Adding test signals and verifying outputs in Signal tap Logic analyzer
- Building board support package (bsp) in NIOS-II, read and write through UART
- Interfacing: Interfacing high speed serial communication protocols (UART, I2C, SPI), External memory interface (EMIF), Memories (DDR3, DDR4, QDR) and Ethernet (10Mbps/100Mbps/1G)
- System Integration and functionality: Integration of PCBs in chassis and verifying functionality
- Technical Documentation: preparing Acceptance Test Procedure (ATP), Production Test Procedure (PTP), Qualification Procedure (QTP) and Technical Manual (TM)
- EMI / EMC: Conducted emissions, conducted susceptibility, radiated emissions and radiated susceptibility
- Environmental Stress Screening (ESS): Random vibration (X-axis, Y-axis and Z-axis), Thermal cycling and burn-in test.
Electronics Corporation of India Limited (ECIL)
09.2020 - 03.2021
- Analyzing datasheets, schematic design: generating netlist and Bill of Materials (BOM)
- Testing and troubleshooting PCBs: Physical inspection, continuity check, impedance measurement, current sense analysis for the core voltages, voltage measurements at test points, reset and clock measurement using Oscilloscope
- RTL Design: Synthesis, simulation, timing analysis and power optimizations
- Technical Documentation: preparing Acceptance Test Procedure (ATP), Production Test Procedure (PTP).
Electronics Corporation of India Limited (ECIL)
10.2019 - 02.2020
- Analyzing datasheets, schematic design: generating netlist and Bill of Materials (BOM)
- Testing and troubleshooting PCBs: Physical inspection, continuity check, impedance measurement, current sense analysis for the core voltages, voltage measurements at test points, reset and clock measurement using Oscilloscope
- Technical Documentation: preparing Acceptance Test Procedure (ATP), Production Test Procedure (PTP).
Hardware Design Engineer
Technospirit
Hyderabad, TG
01.2018 - 10.2019
- Analyzing datasheets, schematic design: generating netlist and Bill of Materials (BOM)
- Testing and troubleshooting PCBs: Physical inspection, continuity check, impedance measurement, current sense analysis for core voltages, voltage measurements at test points, reset and clock measurement using Oscilloscope
- PCB Design: Basic level 2-layer PCB design
- RTL Design: Verilog coding, Simulation, synthesis and timing analysis.
Education
M. Tech - Microelectronics & VLSI Design
Indian Institute of Technology (IIT), Madras
Chennai, TN11.2017
B. Tech - Electronics and Communication Engineering
National Institute of Technology (NIT), Agartala
Agartala, TR05.2014
12Th - MPC
NAVEENA JR. COLLEGE, R.R DIST.
Hyderabad, TG04.2009
10Th - ALL
JAWAHAR NAVODAYA VIDYALAYA, VATTEM
Mahbubnagar, TG05.2007
Skills
- Hardware Description Language : Verilog and VHDL
- Programming Language : C
- FPGA Development Tool : INTEL Quartus prime, XILINX VIVADO, VIVADO HLS
- Schematic Design : Cadence ORCAD capture
- PCB Layout Review : Cadence Allegro Physical viewer
- MATLAB : MATLAB and SIMULINK basics
Languages
English
Hindi
Telugu
Strengths And Competency
- Team facilitator
- Creative, adaptable, amicable and an ultimate learner
- Good Communication Skills
- Analytical decision maker with good problem solving, motivating skills and good team player
Scholastic Achievements
- Acquired All India Rank 386 in GATE 2015
- Qualified GATE in all the attempts in the years: 2014, 2015, 2017, 2018, 2019
- College topper in intermediate with 96.60 percentage
- Secured medals in school cluster games
- Ranked CPL in NCC (A-certificate)
Personal Information
- Father's Name: SHAKRU
- Mother's Name: B RANGI
- Date of Birth: 04/17/91
- Gender: Male
- Nationality: Indian
- Marital Status: Married
Academic Non Academic Projects
- Design and implementation of Single Carrier-Frequency Division Multiple Access (SC-FDMA) Modem, May 2016 - June 2017, Dr. Nitin Chandrachoodan, IIT Madras, XILINX ISE, VIVADO, VIVADO HLS, Cadence RTL Compiler, The aim of this project is to design and develop a Single Carrier Frequency Division Multiple Access (SC-FDMA) transmitter and receiver(modem). This project is simulated and synthesized on FPGA board (Vertex VC- 707). Timing constraints are added to verify the static timing analysis to overcome metastability and also power optimizations are performed.
- Emergency messaging system with antenna shocking mechanism, June 2013 - May 2014, Biman Debbarma, NIT AGARTALA, The aim of this project is to design an emergency messaging system and an antenna is embedded within the design. When someone attacks, this antenna can be used for giving shock to the person who attacks.
Industrial Projects
- 1Kw 27.12MHz Class-E Solid State Power amplifier, Bhabha Atomic Research Centre (BARC), Mumbai, C.I Sujo (Scientific officer-F), BARC Mumbai, Genesys, The aim of this project is to design a class-E solid state power amplifier using the concept of 'Maximum power Transfer theorem'. Source impedance is matched with load impedance, so that maximum power can be transferred from source to load to attain maximum efficiency.
- Design of Watch antenna, IISc, Bangalore, K J Vinoy, IISc Bangalore, The aim of this project is to design a watch antenna using microstrip patch antenna and antenna is embedded within the watch.
Hobbies and Interests
- Reading books
- Playing and watching cricket
Disclaimer
I hereby declare that above mentioned details are genuine.
Timeline
Project Engineer
Bharat Electronics Limited (BEL)
04.2021 - Current
Electronics Corporation of India Limited (ECIL)
09.2020 - 03.2021
Electronics Corporation of India Limited (ECIL)
10.2019 - 02.2020
Hardware Design Engineer
Technospirit
01.2018 - 10.2019
M. Tech - Microelectronics & VLSI Design
Indian Institute of Technology (IIT), Madras
B. Tech - Electronics and Communication Engineering
National Institute of Technology (NIT), Agartala
12Th - MPC
NAVEENA JR. COLLEGE, R.R DIST.
10Th - ALL
JAWAHAR NAVODAYA VIDYALAYA, VATTEM
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