CHANDU HARSHA LETI
Nellore
Summary
As a Layout Designer by working in a service based company i had the opportunity to work in multiple projects and explore the different technology nodes like 3nm, 7nm, 5nm 45nm, 180nm etc, but I thrive to learn and explore more in this domain as i grow in my career. I have created the quality and manufacturable layouts in on time with my problem solving skills and wishing to continue more.
Overview
2
2
years of professional experience
Work History
Analog Layout Design Engineer
Capgemini
08.2022 - Current
- Successfully completed multiple tape-out projects by adhering to strict quality standards and design specifications.
- Delivered optimal solutions for complex routing problems through meticulous planning and innovative approaches.
- Managed project timelines effectively, ensuring on-time delivery of high-quality layouts that met customer requirements.
- Ensured robustness of designs through thorough verification using industry-standard tools and methodologies.
- Improved design efficiency by implementing automation techniques in analog layout processes.
Education
Bachelor of Technology - Electrical, Electronics And Communications Engineering
Presidency University
Bengaluru, India06.2022
Skills
- CMOS Technology IC Fabrication Latch-up Matching Antenna Effect Electromigration IR Drop Parasitic Extraction
- Virtuoso Cadence layout XL Editor EXL Editor
- Scripting languages-Perl and Python
- Analog Circuit Design
- CAD Tool Proficiency
- Design Rule Checking
- LVS (Layout versus Schematic)
- RV Extraction
- Floorplanning Techniques
- EMI Shielding Techniques
- Cross-talk Reduction
- Schematic Interpretation
- Power distribution techniques
- Proficient Communication / Interpersonal Skills
- Efficient Leadership / Team Management & Presentation Skills
Projects
Intel 7nm - GDDR7 P1276 : Contributed to tasks like DRC & LVS flow changes and fill related changes
ATTD_MAKHILL - 22 nm : Worked on Via and DRC changes
Barak - 5 nm : Worked on multiple sub-blocks by Floor-Planning, Placement and Routing.
Timeline
Analog Layout Design Engineer
Capgemini
08.2022 - Current
Bachelor of Technology - Electrical, Electronics And Communications Engineering
Presidency University