Yuga Venkata Narayana Maruboina
Machilipatnam
Summary
Seeking a responsible job with an opportunity for professional challenges. Flexible hard worker ready to learn and contribute to team success.
Overview
3
3
years of professional experience
Work History
Analog Layout Engineer
Moschip Technologies
04.2021 - Current
Oscillator: (3 Months)
Technology: 65nm (TSMC)
Worked on Schematic design changes.
Taken care of routing plan and power plan.
Worked on DRC and LVS and antenna check
Band Gap Reference:
Technology: 28nm (TSMC)
➢ Worked on the layouts from initial floorplan and complete responsible for Diff op-amp, Resistor network and BJT Matching
➢ Taken care on floorplan i.e placing the resistor and BJT away from the OP-Amp.
➢Taken care symmetry routing in Op-Amp and Match the resistors and BJTS in 1:8.
➢ Clean the all verification checks i.e DRC, LVS, ERC, EM, IR and Antenna errors.
PLL:
Technology: 12nm (TSMC)
Worked on Divider.
Layout Design & Verification
Taking Care of Parasitic, Maintaining Signal Flow
Worked on post simulation changes and cleared DRC and LVS.
DDR-IO:
Technology: 5nm (SS),22nm (intel)
Worked on supporting ios .
Layout Design & Verification
Taking Care of ESD Diode placement and routing,
Worked on EM,IR and density clean.
RX:
Technology: 7nm,5nm,3nm (TSMC)(SS)
Worked on top level and sub blocks like Bias ans OP-AMP .
Layout Design & Verification.
Worked on EM,IR and density clean
TX:
Technology: 7nm,5nm,3nm (TSMC)(SS)
Worked on blocks like TX top level , Driver level and its sub blocks.
Taking Care of ESD Diode placement and routing
Layout Design & Verification.
Worked on EM,IR and density clean
GDDR-IO:
Technology: 5nm (SS),3nm(TSMC)
Worked on common .
Layout Design & Verification
Taking Care of PLL_ANACLK,Bias signals and PAD Routigs.
Worked on EM,IR and density clean
RX:
Technology: 3nm,5nm,7nm (TSMC)
Worked on sub blocks like Bias ans OP-AMP .
Layout Design & Verification.
Worked on EM,IR and density clean
TX:
Technology: 7nm 5nm,3nm (TSMC)
Worked on blocks like TX top level , Driver level and its sub blocks.
Taking Care of ESD Diode placement and routing
Layout Design & Verification.
Worked on EM,IR and density clean
Analog Layout Trainee
Moschip institute of Silicon Systems
12.2020 - 03.2021
Technology: 45nm & 90nm (TSMC)
Worked on op-amp and Standard cell layout design.
Worked on SRAM layout design.
Worked on Verifications DRC and LVS.
Education
Electronics and Communication Engineering
DMS SVH College of Engineering
Machilipatnam04.2019
Diploma - Applied Electronics and Instrumentation Engineering
AANM & VVRSR Polytechnic
Gudlavalleru04.2016
ST.Francis High School
Machilipatnam04.2011
Skills
- 3 years of experience in Analog Mixed-signal layout
- Understanding of Deep submicron effects and Advanced tool usage, floor planning, routing techniques, Power planning
- Good understanding of Planar and FINFET layouts and processing technology in 90nm, 65nm,40nm, 28nm, 22nm,16nm, 12nm, 7nm, 5nm, 3nm
- Good understanding of basic ESD, antenna and latch up layout design considerations
- Good knowledge in clearing of minimum and maximum density issues, DRC, LVS, ERC, DFM, EM & IR etc in block level
- Familiar with Parasitic extraction and matching techniques, symmetry for differential op-amp, current mirror, LDO & shielding of critical nets
- Good written and verbal communication skills in interactions with internal development teams, and customers
Tools Technical Skills
- Layout Tools: Cadence Virtuoso - XL, LE
- Layout Verification Tools: Calibre,PVS(Pegasus),ASSURA,voltus.
- Working knowledge in MS OFFICE.
Disclaimer
I hereby declare that the above-mentioned details are true to the best of my knowledge.
Languages
Telugu
First Language
English
Upper Intermediate (B2)
B2
Hindi
Intermediate (B1)
B1
Timeline
Analog Layout Engineer
Moschip Technologies
04.2021 - Current
Analog Layout Trainee
Moschip institute of Silicon Systems
12.2020 - 03.2021
Electronics and Communication Engineering
DMS SVH College of Engineering
Diploma - Applied Electronics and Instrumentation Engineering
AANM & VVRSR Polytechnic
ST.Francis High School
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