Nagulla SubbaRao
Warangal
Summary
Skilled in Analog Layout Design Engineering with focus on developing complex analog and mixed-signal integrated circuits. Strong background in various technologies including CMOS, BiCMOS, and SiGe. Understands design rules, device matching, low power techniques, parasitic reduction strategies and floor planning. Proven track record of optimizing designs for performance, manufacturability and testability.
Overview
3
3
years of professional experience
Work History
Analog Layout Design Engineer
NIT Warangal
Warangal
11.2023 - Current
- Hand on experience in planner and fintech technology. TSMC 180nm BCD, 65nm, 28nm, 16nm; UMC 180nm CMOS, 65nm; SCL 180nm; SBC TOWER SEMICONDUCTOR 135nm, and GPDK 90nm, 45nm.
- Conducted rigorous DRC checks on layouts by using caliber tools for adherence to specifications.
- Maintained detailed documentation of design modifications for effective traceability.
- Created layouts for various blocks, including LDOs, BGRs, DC-DC converters, and temperature sensors.
- Utilized advanced machining techniques like interdigitation and common centroid to enhance designs.
- Successfully completed TAPOUT for SCL 180nm and fabricated in shuttle II, worked from block level to chip level by reducing layout-dependent effects such as STI, WPF, and EMIR drops.
- Provided technical support to customers regarding analog design implementation issues.
Custom Layout Engineer
sumedha it
Hyderabad
10.2022 - 10.2023
- Focused on analog layout creation for TSMC 28 nm and 16 nm process nodes.
- excellent knowledge flow of ASIC design fabrication steps
- Completed half DRC and full DRC reviews for various digital components.
- Identified layout-dependent effects like STI, LOD, WPF, latch-up, cross talk, dummy filling, and double patterning.
- Done all block in PLL using TSMC 16nm, and maintained layout dependent effects
Education
Post-Graduate - EMBEDDED SYSTEMS
Dr. Paul Raj Engineering College
Yatapaka, Andhra Pradesh07-2025
Bachelor of Technology - Electronics And Communications Engineering
UNIVERSAL COLLEGE OF ENGINNERING AND TECHONOLGY
PERECHERLA 05-2017
Board of Intermediate Education Andhra Pradesh - MPC
Sri Chaitanya Junior College
GUNTUR 04-2013
SSC - 10TH
APPLE CONCET SCHOOL
PERECHERLA 03-2011
Skills
- Layout design and optimization
- ASIC design and integration
- EMI shielding and cross-talk reduction
- RF layout techniques and guard ring implementation
- Advanced process nodes and parasitic extraction
- Mixed-signal layout techniques
- Substrate noise mitigation and latch-up prevention
- Device matching techniques and design rule checking
- Scripting languages for automation
Languages
Telugu
First Language
English
Upper Intermediate (B2)
B2
Hindi
Beginner (A1)
A1
Timeline
Analog Layout Design Engineer
NIT Warangal
11.2023 - Current
Custom Layout Engineer
sumedha it
10.2022 - 10.2023
Post-Graduate - EMBEDDED SYSTEMS
Dr. Paul Raj Engineering College
Bachelor of Technology - Electronics And Communications Engineering
UNIVERSAL COLLEGE OF ENGINNERING AND TECHONOLGY
Board of Intermediate Education Andhra Pradesh - MPC
Sri Chaitanya Junior College
SSC - 10TH
APPLE CONCET SCHOOL