CHARANPREET SINGH
Semiconductor - Verification and Validation Lead
Bengaluru,Karnataka
Summary
OUTLINE
Result-oriented professional with 14 years of experience in the System Integration, Validation, Emulation and Hardware
technologies for range of SoC design solutions with proven track in enabling system integration, system bring-up, debug
and validation solutions for ever-growing complex scenarios.
Overview
14
14
years of professional experience
6
6
years of post-secondary education
Work History
Principal Engineer
Arm India
Bangalore, Karnataka
03.2022 - Current
- Leading a team of 40 members building mini SoC design building targeted for Infra, Server, Networking, Premium Mobile, Low-End Mobile, Large Screen Compute, Auto, IoT based solutions.
- Empowered first bring-up of multiple IPs catering to various market segment in system world.
- Persistent delivery of configurable and scalable platform solutions for functional stress validation, performance analysis studies, OS readiness, Emulation and FPGA compliant designs.
- Enriched experience of enabling multiple IPs across various class of CPU, GPU, System Interconnect and controllers, PCIe, CXL, Memory Controllers.
- Enabled strengthened validation suite catering to dynamic system handling with good smoke coverage.
- Worked on enabling end-to-end automation framework with a layer of user-interface to configure IP rendering parameters to auto-stitching for RTL to test regression identification and execution.
- Recognized trail of collaborating with diverse stakeholders, aligning deliverable timelines and handling dynamic change requests with minimal impact on schedules.
Staff Application Engineer
Synopsys India Pvt. Ltd
, Delhi
01.2015 - 01.2022
- Recognized by executive management for building excellent relationships with top accounts and industry partners and for positioning solutions versus leading competitors.
- Empowered multi-million SoC designs for Server, Mobile, IoT, Automobile applications on emulation platforms.
- Appraised and validated Simulation Acceleration and Emulation bring-up for range of customer designs.
- In-depth understanding for different phases of Emulation bring-up flow vizCompile, run, debug, performance.
- Bring-up of Power Estimation scenarios on Emulation platforms for Power-Aware Software development.
- Facilitated bring-up and debug of various interfaces as transactors and memory models.
- Intelligent Debug solution for multi-Billion gate designs enabling multi-interface debug through interactive control and filter mechanism for monitors extending up to performance evaluations.
Senior Engineer
Qualcomm India Pvt. Ltd
, Karnataka
11.2012 - 07.2015
- Aided Emulation flow enhancements and deployment in Qualcomm for smart phone chipset solutions
- Enabled Gate-Level Simulation on Emulators
- Experience in deploying design specific solutions for 10 Emulation SoCs and their derivatives at Qualcomm
- Kindled Qmemgen memory generation tool for Emulation and Simulation Acceleration platforms, enabled multiport design on BRAM, enhancing bit-addressable memory implementation enabling 40% resource reduction
- Enabling the Smart Scheduler for Optimal usage of various Emulation platforms (Veloce Enterprise Server,Palladium HRM, RUMI Farm UI)
- Enabled the FPGA health-check channel to monitor critical operational parameters, bit-file version tracking to intercept hardware or user issues.
Assistant Professor
Chitkara University
, Punjab
01.2011 - 01.2012
- Tutored courses on Digital Electronics, C++ Programming and VLSI
- Section In-charge of Centre of Excellence (VLSI and Embedded).
Product Validation Consultant, Encounter Test
Cadence Design Systems
09.2010 - 01.2011
- Familiarity in validation of Encounter Test tool to enable “Design for Testability” in designs
- Generated Perl based Automation of Regression Validation Flow.
Education
Master of Technology - VLSI Design and CAD
Thapar University
07.2008 - 06.2010
Bachelor of Technology - Electronics and Communication
Punjab Technical University
08.2004 - 06.2008
Skills
- ZeBu / Palladium / Veloce
- Infra / Client / Auto / IoT Solution Architecture
- Automation
- Systwm Verification and Validation
- HDLs
- TCL / Perl / Python / C / C
- Xilinx FPGA
- VCS / Questa / Visualizer / Verdi
- Power Estimation
- GL Emulation
- System Debug
- SoC Bring-Up
- Simulation Accel
- Transactors
- Performance
- Monitors
- System Architecture
- Solution Building
- Cross-Functional Collaboration
Timeline
Principal Engineer
Arm India
03.2022 - Current
Staff Application Engineer
Synopsys India Pvt. Ltd
01.2015 - 01.2022
Senior Engineer
Qualcomm India Pvt. Ltd
11.2012 - 07.2015
Assistant Professor
Chitkara University
01.2011 - 01.2012
Product Validation Consultant, Encounter Test
Cadence Design Systems
09.2010 - 01.2011
Master of Technology - VLSI Design and CAD
Thapar University
07.2008 - 06.2010
Bachelor of Technology - Electronics and Communication
Punjab Technical University
08.2004 - 06.2008
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