NAMIT JAIN
Lead Senior Engineer
Bangalore,KA
Summary
Driven and detail-oriented SoC Verification Engineer with a strong foundation in SoC infra IPs. My expertise spans protocol-level debug, infra IP validation & performance analysis. I thrive in fast-paced environments where precision, collaboration, and innovation are key to delivering high-quality silicon. Passionate about solving deep system-level challenges and contributing to cutting-edge SoC development, I aim to grow with a forward-thinking organization that values technical excellence and continuous learning.
Overview
10
10
years of professional experience
8
8
Certifications
2
2
Languages
Work History
Lead Senior HW Engineer
Qualcomm India Pvt Ltd
01.2020 - Current
- Tasks:
- Functional Validation
- Pre and Post Si Validation: Validation on bare metal as well as RUMI FPGA platforms for Premium Tier SoCs.
- Ownership of Infra NoC, mi_PMU, QMIP, and ADCVS IPs validation.
- Verification Platforms: Utilized RUMI FPGA and Veloce platforms for PreSi Verification.
- Test Content Development: Developed test content in Embedded C for Infra NoC, mi-PMU, and QMIP exposed 14 HW bugs so far in 4 SoCs.
- Adaptive Bus DCVS: Enabled Adaptive DCVS in SVE for GPU rails for Shub and MC Hardening.
- Debugging Expertise: Participated in multiple debugs, bringing expertise to reduce turnaround time (TAT).
- Performance Validation
- Multimedia Use Cases: Tuned the system for multimedia-centric use cases where Camera Display Video cores are involved to improve SoC performance.
- Peripheral Performance Validation: Worked on validating the performance of various peripherals IPs like PCIe, IPA, QSPI.
- CPU Performance: Developed and published CPU performance KPIs using lmbench and bwmem tests.
- SoC Performance Framework: Created a framework to enhance performance validation coverage with sweeping through different irritators like QoS, SMMU parameters, DDR freq etc.
- DoU Optimization: Focused on DoU power/performance optimization.
Senior Embedded Engineer
KPIT Technologies
01.2018 - 01.2019
- Tasks:
- Part of Product Engineering Services (PES) for Embedded Software Development.
- Reduced CPU load by distributing OS, RTE, DEM, XCP and FIM Modules on dual core. Throughput calculation and Optimization of Standard APIs. Multi-core BSW distribution.
- Automation of Development process in GitLab using python script. Python Tool Development for Code Assessment.
Embedded System Engineer
TATA Engineering Services
01.2016 - 01.2017
- Tasks:
- Embedded-C based Diagnostic stack development as per AUTOSAR for Japanese OEM.
- Unit testing, Module testing and Integration testing for complete stack as per client requirement.
- Participated in multiple debugs and issues raised by client.
Education
Bachelor of Technology - Electronics and Communication Engineering
Institute of Technology, Nirma University
05-2016
AISSCE - Physics Chemistry Mathematics
Kendriya Vidyalaya
01.2011
Skills
SoC Architecture
Performance Optimization
NoC Protocol & Memory Subsystem Analysis/ Debug
Linux / Embedded C / C / system verilog / python
ARM AMBA Protocols - AXI/ AHB/ CHI/ ACE
Lauterbach T32 / JTAG Debugging / Waveform Analyzer
Infra Design Verification
Emulation & Post Si verification
Veloce/ ZeBu/ Rumi platforms
Shell / bat / cmm scripting
Performance analysis for MSM/ Server/ Compute chipset
GIT/ Perforce/ Sharepoint
Certification
Hardware Team Annual Impact Award 2023. (QUALCOMM)
Timeline
Lead Senior HW Engineer
Qualcomm India Pvt Ltd
01.2020 - Current
Senior Embedded Engineer
KPIT Technologies
01.2018 - 01.2019
Embedded System Engineer
TATA Engineering Services
01.2016 - 01.2017
AISSCE - Physics Chemistry Mathematics
Kendriya Vidyalaya
Bachelor of Technology - Electronics and Communication Engineering
Institute of Technology, Nirma University