Devi Sathya G
Bangalore
Summary
Design Verification Engineer with 7 years of experience in building verification environments. proficient in AMBA AHB, APB, Data fabric , PCIe protocols with strong expertise in System Verilog and UVM methodology. Experienced in IP and subsystem-level verification, assertion-based verification, and coverage closure using standard simulation tools such as VCS and Verdi.
Overview
8
8
years of professional experience
Work History
Data Fabric
AMD
02.2022 - Current
- Executed fabric/interconnect verification by validating data flow, cache coherency
- Revamped UVM testbench, supporting new features and increasing functional coverage
- Resolved regression failures, enhancing software reliability and ensuring consistent performance
- Developed and executed comprehensive testcases, achieving verification closure through effective use of coverage metrics
Host Interface (HIF)
WIPRO
Banglore
11.2020 - 02.2022
- HIF provides connectivity infrastructure between NIC devices and host systems. HIF will interface directly with protocol engines such as LAN, RDMA, NVMe, LCE and arm compute complex. The host interface will manage PCIe configuration space and provide flexibility in assigning NIC sources across multiple functions and hosts. HIF will provide the PCIe TL layer management, various DMA services. It will also provide interfaces to manage transactions targeted towards devices connect off the PCIe root port.
- Developed PCIe error injection scenarios to validate system resilience under fault conditions.
- Created test cases and sequences to validate system functionality and performance.
- Designed and integrated callback functions to enhance system interactivity and responsiveness.
- Developed and implemented callbacks and checkers.
- Analyzed test case failures, submitted HSDs for RTL issues, and provided thorough root cause analysis.
- Created Cadence ticket cases for VIP issues, detailing comprehensive analysis to facilitate resolution.
Gunderson Rock (GDR)
INTEL
Banglore
03.2019 - 10.2020
- GDR PCIe IP core is part of Intel’s F-Tile CHIP of EMIB technology, which is embedded with 4 cores to support 1x16, 2x8, 4x4 topologies and can act as End Point and Root Port. The highest supported rate is Gen4 and verified with PIPE level. The bench is integrated with Dual VIP test suites with Avery and Synopsys to ensure the compatibility and high-level functional checks.
- Handled TL/DL layer Synopsys testsuite tests running on INTEL PCIe Gen4 IP core.
- Debugged regression failures, implementing effective fixes to enhance overall functionality.
- Submitted HSDs for RTL issues, delivering comprehensive debug analysis to facilitate resolution.
- Worked on implementing logics for atomic operations and TLP Driver in Intel Testbench.
- Submitted Solvent Cases for VIP/Testusite issues, detailing analysis of mismatches with test intent.
- Resolved Intel’s testbench issues by applying forces for RTL signals, ensuring compatibility between DUT and VIP.
- Worked on random seed failures and provided the fixes for clean closure of RTL1.0 release.
- (Wipro)
RAL Integration for Legacy Projects
AdeptChip
Banglore
11.2018 - 03.2019
- Ral Model simplifies the register verification of ASIC Designs. A register model is an entity that encompasses and describes the hierarchical structure of class objects for each register and its individual fields.
- Integrated RAL model into legacy UVM environment by developing adaptor based on register specification.
- Developed scenarios for back door and front door access to DUT registers, enhancing testing capabilities.
- Created scenarios using inbuilt RAL sequences like bit bash etc.
- Added options to enable the RAL coverage.
- Collaborated with Bangalore ODC team to streamline workflows and optimize project outcomes.
APB Master BFM Development
SocBridge Semiconductors Pvt Ltd
06.2018 - 11.2018
- APB stands for Advanced Peripheral Bus. The APB is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. APB is non-pipelined protocol. APB is mainly optimized for minimal power consumption, reduced interface complexity and low bandwidth control access.
- Implemented APB master environment including driver and monitor, ensuring compliance with APB protocol specifications.
- Developed verification plan and architected SV and UVM based verification environment to ensure robust testing framework.
- Porting of SV based BFM in to UVM.
- Involved in creation of Assertion and coverage plans.
- Worked on implementing the assertions and coverage.
- Implemented Scoreboard and other components from the scratch.
- Created scenarios to verify functionalities of single and back-to-back transactions, assessing performance under various wait state conditions.
- Worked in Bangalore
AHB Master Development
SocBridge Semiconductors Pvt Ltd
Banglore
06.2018 - 11.2018
- AHB implements the features required for high-performance, high clock frequency systems including burst transfers, single-clock edge operation, non-tristate implementation, wide data bus configurations, 64, 128, 256, 512, and 1024 bits.
- Developed verification plan and architected SV and UVM based verification environment to enhance testing efficiency.
- Implemented AHB master environment with driver and monitor, ensuring compliance with AHB protocol.
- Executed assertions and coverage implementation to improve verification accuracy.
- Involved in creation of Assertion and coverage plans.
- Creation of scenarios to verify the functionalities including single transactions and back-to-back transactions with and without wait states.
- Implemented Scoreboard and other components from the scratch.
- Porting of SV based BFM in to UVM.
- Worked in Bangalore
Education
B.Tech - Electrical & Communication Engineering
N.B.K.R Institute of Science and Technology
VidyanagarSkills
- Verilog
- SystemVerilog
- UVM
- PCIe
- AMD Infinity Fabric
- APB
- AHB
- VCS
- VERDI
- QUESTASIM
Accomplishments
Spotlight Award Q4,2024
Timeline
Data Fabric
AMD
02.2022 - Current
Host Interface (HIF)
WIPRO
11.2020 - 02.2022
Gunderson Rock (GDR)
INTEL
03.2019 - 10.2020
RAL Integration for Legacy Projects
AdeptChip
11.2018 - 03.2019
APB Master BFM Development
SocBridge Semiconductors Pvt Ltd
06.2018 - 11.2018
AHB Master Development
SocBridge Semiconductors Pvt Ltd
06.2018 - 11.2018
B.Tech - Electrical & Communication Engineering
N.B.K.R Institute of Science and Technology