Dhavalsinh Sajjansinh Ravalji

Dynamic professional seeking to contribute to a progressive organization that fosters growth and innovation. Eager to leverage skills while continuously developing expertise to drive organizational objectives forward. Committed to achieving career goals in alignment with the company’s vision, ensuring mutual success and advancement. Passionate about creating impactful results within a collaborative and challenging work environment.

Dhavalsinh Ravalji and Rajnikant Soni “ Simulation And Characterization Of Voltage Follower For Class-A topology in CMOS 180 nm Technology” at International Journal Of Engineering Science & Research Technology, vol. 3 Issue, ISSN:9277-9655.

• Attended ISTE Approved National Workshop on ASIC & FPGA Design flow on 30-31 august, 2013.
• Active member at Faculty development Program for design engineering course at Gujarat Technological University.
• Performed Duty as Flying Squad as well as Observer at GTUZone-3.
• Appointed as verification Officer from Admission committee for professional courses, GTU.
• One Month training at Matrix Telecom – Vadodara
• One day visit at Infosys –Chandigarh
• Visited Institute of plasma research, Bhatt Village, Gandhinagar.

• Office Suits
• Email and Internet
• File Management
• Communication Tools
• Operating System