FIROZ S. SATHAWANE
Bangalore
Summary
Dynamic Application Engineer with extensive experience at Siemens, specializing in FPGA prototyping and emulation. Proven track record in PCIe and Ethernet bring-up, delivering effective customer support and innovative solutions. Proficient in TCL scripting and Verilog programming, I excel in collaborating with teams to enhance product performance and resolve complex issues.
Overview
8
8
years of professional experience
Work History
Application Engineer
Siemens
10.2022 - Current
- Working on FPGA bring-up, bitfile programming, and deployment over PCIe and Ethernet
- Debugged PCIe and Ethernet connectivity issues between Host PC and FPGA blades, ensuring reliable communication and system performance
- Analyzed timing violations (WNS/TNS) and evaluated multiple placement/routing strategies, contributing to improved target frequency and overall design efficiency
- Supported customers with proFPGA and proFPGA_CS platforms, optimizing multi-blade setups and clock distribution.
- Generating and managing CFG, PHD, and TCL files using RED tool flows
- Investigating system issues such as high CPU usage, slow read/write performance, and reboot loops
- Collaborated with R&D teams to clarify tool limitations and planned features, delivering effective workarounds.
- Provided customer-ready debug summaries and root-cause analyses, offering actionable guidance for issue resolution.
- Executed debug and trace flows using Redview, probes, and probeless trace.
SENIOR ENGINEER
TechM Cerium Semiconductor
06.2021 - 10.2022
- Implemented VIRTIO mechanism to facilitate DMA memory communication with PCIE end users via AXI and Avalon interfaces.
- Delivered Spyglass CDC support for multiple IPs.
- Modified .tcl script and .v file for IP GUI enhancements, provided LZ support, and resolved HSD-related issues to improve user experience.
- Supported IP workbase at Intel, ensuring seamless operations and project alignment.
- Collaborated on Quartus and QuestaSim projects to streamline design workflows and improve project outcomes.
SENIOR ENGINEER
Tessolve Semiconductor
07.2020 - 05.2021
- Developed .tcl scripts and .sv files for test case generation, regression execution, and IP support enhancement.
- Validated Ethernet IP, providing critical support at client site Xilinx Hyderabad.
- Conducted validation on VIVADO and Viper flow regression, ensuring system reliability.
- Identified and categorized IP types including MRMAC, DCMAC, and l_ethernet for project documentation.
SENIOR ENGINEER
Tata Elxsi
Bangalore
10.2017 - 12.2019
- Design and implementation of architecture of Automatic Factory Vehicle(AFV).
- Design, test and deliver a fully functional AFV prototype.
- Bring up FPGA board, FPGA Validation and functionality testing of individual sensors/peripherals.
- Achieved timing closure for RSCAN design by analyzing and optimizing signal pathways.
- Ensured thorough project understanding and adherence to timing requirements.
- Reviewing Timing Summary report to evaluate timing throughout the flow.
- Focus on worst negative slack (WNS) of each clock as the main way to improve total negative slack (TNS).
- Utilized tool options and Xilinx design constraints (XDC) to optimize design processes.
- Employed pipeline architecture to enhance performance of critical timing path.
- Designed and implemented a 4Kp60 video capture card (UHDC-T3).
- Performed testing of completed hardware on FPGA Board Kintex UltraScale FPGA KCU105 and used a Chip-scope and Logic Analyzer.
Education
Post Graduation Diploma - VLSI Design
CDAC ACTS
Pune01-2016
B.E. - Electronics And Telecommunication
J.D. College Of Engineering
Nagpur07-2015
H.S.C. -
Vidarbha Buniyadi Jr. College
Nagpur08-2010
S.S.C. -
Vidarbha Buniyadi HIgh School
Nagpur07-2008
Skills
- FPGA prototyping and emulation
- Verilog programming
- Vivado proficiency
- PCIe and Ethernet bring-up
- AXI protocol expertise
- ILA and ChipScope usage
- ModelSim debugging
- Questa simulation
- Bitfile generation
- TCL scripting
- VPS tools
- Linux and Unix shell scripting
- Blade configuration
- Technical documentation
- Linux and Unix shell scripting
Accomplishments
- Attend the Workshop of Electronics Component Identification and Testing conducted by J.D.college of Engineering - 2nd winner.
- Participate in 'VIBRANCE-2K14' – Roborace - 2nd winner.
Additional Projects
- Glowing Tube light using waste CFL Compact Fluorescent Bulb.
- Glowing fuse waste Tube light using Bridge rectifier.
- Generate electricity by walking using Piezo electric material.
Languages
English
Intermediate (B1)
B1
Hindi
Intermediate (B1)
B1
Marathi
Intermediate (B1)
B1
Timeline
Application Engineer
Siemens
10.2022 - Current
SENIOR ENGINEER
TechM Cerium Semiconductor
06.2021 - 10.2022
SENIOR ENGINEER
Tessolve Semiconductor
07.2020 - 05.2021
SENIOR ENGINEER
Tata Elxsi
10.2017 - 12.2019
Post Graduation Diploma - VLSI Design
CDAC ACTS
B.E. - Electronics And Telecommunication
J.D. College Of Engineering
H.S.C. -
Vidarbha Buniyadi Jr. College
S.S.C. -
Vidarbha Buniyadi HIgh School