Gopinath Reddy Devireddy

11 Years of in-depth Experience in DFT implementation, DFT CAD and post silicon activities. Hands on experience on complete DFT cycle which includes PLDRC, RTL level insertion using Tessent SSN test solution, dfstitich using FC/DC tool, FV, CLP, ATPG, Test Coverage Analysis and Simulations. Lead DFT implementation for few subsystems like DDR, Audio, Camera and Tiles in five premium tier projects. Worked closely with cross-functional teams to make DFT scalable and compatible across ASIC cycle. Have exposure to post silicon activities on ATE tester. Currently working as a part of GCAD team, supporting dfstitich flow using FC and RTL insertion flow using mentor SSN test solution.

Qualcomm Technologies Pvt Ltd, Bangalore [Jan2019 to Present], Joined as Senior DFT Engineer and got promoted to Staff Engineer. 

      1. Project Name: Project1(2019): Spyglass DFT DRC checks, DDR and AUDIO cores scan insertion at Gate level using DC tool, Stuck at ATPG Pattern generation, Test Coverage Improvement, FV and CLP clean up, No-timing simulations

      2. Project Name: Project2(2020): Spyglass DFT DRC checks, DDR and AUDIO cores scan insertion at Gate level using DC tool, Stuck at ATPG Pattern generation, Test Coverage Improvement, FV and CLP clean up, No-timing simulations

      3. Project Name: Project3(2021): Spyglass DFT DRC checks, DDR and AUDIO cores LSDFT IP’s insertion at RTL level, Scan chain stitching at gate level, Stuck at ATPG Pattern generation, Test Coverage Improvement, FV and CLP clean up, No-timing simulations

      4. Project Name: Project4(2022): Spyglass DFT DRC checks, DDR and AUDIO cores LSDFT IP’s insertion at RTL level, Scan chain stitching at gate level using single dictionary based across different synthesis tool, Stuck at ATPG Pattern generation, Test Coverage Improvement, FV and CLP clean up, No-timing simulations

      5. Project Name(2023 to present): Tessent LeftShift DFT RTL insertion and DC/FC flow support role in GCAD team

ALTRAN TECHNOLOGIES INDIA, Bangalore [Oct2015 to Jan2019], Joined as DFT Engineer and got promoted to Advance DFT Engineer

      1. Project Name: soc1, Intel, Spyglass DFT DRC checks, ATPG Pattern generation (Struck-at, Transition and Cell Aware) at block level, Test Coverage Improvement, Partition level timing and no-timing simulations, Multi-partition level ATPG, Silicon Bring Up

      2. Project Name: soc1, eSilicon, Scan insertion at block level, EDT insertion at block level, ATPG Pattern generation at block levels., Pattern Retargeting from block level to chip level., Formality check at every level of netlist changes., VCS timing & no-timing simulations for ATPG Patterns

      3. Project Name: soc2, eSilicon, ATPG Pattern generation (Struck-at & Transition) at block level, DRC violations Analysis & fixing, Pattern Retargeting from block level to chip level

TESSOLVE SEMICONDUCTORS Pvt Ltd, Bangalore [Nov2013 to Oct2015], ATE Test Engineer

      1. Project Name: MPC8315E UltraFLEX to Tiger Conversion, Client: Freescale Semiconductor, Malaysia., Conversion of MPC8315E testing from high end UltraFLEX tester platform to Low end Tiger tester platform is basically a turnkey project which involves testing of DC parametric tests like Continuity, Leakage, Idd... And interfaces like SPI, I2C, jtag, USB through functionally. Introduced Loopback concept in testing High speed interfaces like SGMII, PCIe, SATA., Application: In Industrial applications like NAS, VoIP, router/gateway, wireless LAN., Role: Involved from program development to program release for production.

• Siemens Tessent streaming scan network Design for Test22.16 level1 certified
• Got best performance certificate on implementing LSDFT insertion on complex cores in Qualcomm
• Secured AIR-5656 in Gate2013.
• Published paper on Practical difficulties to correlate UFlex with Tiger in Tessolve Newsletter Firstbin July2015.
• Got appreciation certificate for the conversion of MPC8315E from Uflex tester platform to Tiger tester platform.
• Got reward in the Tessolve communication protocol program for the presentation given on the interfaces RGMII, SGMII, QSGMII and how they are tested.

• Name : D Gopinath Reddy
• Father’s Name : D Jayarami Reddy
• Date of Birth :1991-10-19
• Permanent Address :3/106, Prakashnagar street, Proddatur, Kadapa-516360, A.P