Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
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Hemant Bhojwani

Bangalore

Summary

  • ASIC Engineer with 3.5 years of experience specializing in IOBIST RTL design and high-speed interface verification using SystemVerilog. Currently at NVIDIA working with GDDR7, Fabric interconnect, PCIe, and XUSB interfaces. Also worked as award-winning engineer with proven track record in performance modeling, architecture exploration, and virtual prototyping at Synopsys.

Overview

4
4
years of professional experience

Work History

Asic Engineer - II

Nvidia
Bangalore
04.2024 - Current
  • Worked with high-speed IO interfaces including PCIe, GDDR7, Fabric Interconnect for next-gen NVIDIA chips
  • Led verification using SystemVerilog and UVM for RTL-level simulation and
  • Contributed to NVIDIA flagship projects: Rubin and Vera architectures with focus on performance optimization
  • Performed RDC/CDC, Lint and Synthesis verification ensuring robust digital design implementation and timing closure

ASIC Engineer - I

Nvidia
Bangalore
04.2023 - 04.2024
  • Implemented RTL design updates for PCIe and USB, and worked to ensure a performance optimization focus.
  • Contributed to NVIDIA flagship projects: Vera, and Thor architectures with focus on performance optimization
  • Executed comprehensive verification using SystemVerilog testbenches and advanced debugging with Verdi

R&D Engineer

Synopsys
Noida
05.2022 - 04.2023
  • Implemented new features like bank map hashing for DDR memories to optimize performance for TLM models
  • Created HBM3 Co-simulation Platform in Platform Architect, improving memory subsystem modeling accuracy
  • Developed Python automation for timing extraction from RTLs using FPGA prototyping, reducing analysis time by 60%

R&D Intern

Synopsys
Noida
12.2021 - 05.2022
  • Performed RTL correlation analysis for DDR and LPDDR memory controllers with SystemVerilog verification
  • Validated SoC system-level cache designs using ARM CHI protocol and analyzed cache efficiency optimization

Education

Bachelor of Technology - Electronics and Communications Engineering

Nirma University
Ahmedabad

Skills

  • RTL design
  • Verilog
  • High-speed interfaces
  • Microarchitecture
  • CDC/RDC
  • LINT
  • Verdi
  • Python
  • Cursor
  • SystemVerilog verification
  • UVM

Accomplishments

Bravo Award Recognized for exceptional contributions to LPDDR5 memory model development and performance optimization - Synopsys Inc.

Spotlight award Awarded for excellence in bringing up co-simulation platform of DW HBM3 IP in Platform Architect - Synopsys Inc.

Timeline

Asic Engineer - II

Nvidia
04.2024 - Current

ASIC Engineer - I

Nvidia
04.2023 - 04.2024

R&D Engineer

Synopsys
05.2022 - 04.2023

R&D Intern

Synopsys
12.2021 - 05.2022

Bachelor of Technology - Electronics and Communications Engineering

Nirma University

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Hemant Bhojwani