HEMANT GEDAM

Results-driven Power and Performance Modelling Engineer at Intel Technology Pvt Ltd India, adept at enhancing VLSI models using Python. Achieved significant improvements in power optimization and system performance through advanced analysis. Proficient in VLSI domain knowledge and skilled in collaborative problem-solving, ensuring high-quality outcomes in complex projects.

• 5G Testbed Physical Layer Optimization (May 2023-June 2024)
  Optimized FAPI uplink modules by analyzing the uplink chain and developing a consolidated Verilog testbench for comprehensive data flow verification.
• 8-bit Signed Carry Save Multiplier (CSM) (July–Dec 2022)
  Designed pipelined and non-pipelined CSMs to demonstrate frequency and data rate improvements. Implemented pipelining with D flip-flops, achieving faster operation Created LVS-clean layout and schematic for logic gates (NAND, AND, inverter, full adder, and CSM).
• VLSI Modeling & Optimization (Jan–May 2023)
  Implemented continuous gate-sizing using GP and MOSEK in Python. Parsed ISCAS-85 Verilog netlists to DAGs, optimized T-Wall delay and area, extracted critical paths, and determined optimal gate drive strengths. Also solved the gate sizing problem using slack.
• CAD for Digital Integrated Circuits (July–Nov 2023)
  Developed efficient Boolean operations using PCR and Bitarray, built ROBDDs with recursive ITE algorithms, and parsed ISCAS netlists. Used DPLL for SAT solving, and Z3 for ILP-based routing optimization Implemented N longest path identification using min-heap and slack.
• Spybot (IV-LAB CLUB)
  Designed and built a surveillance robot for discreet monitoring of suspicious activities. Integrated Raspberry Pi Zero W with a Pi camera, along with DC motors and servo motors for real-time remote operation.

• Digital IC Design
• Analog Electronics circuit
• Computer Organizations and Architecture
• Modelling and optimization in VLSI
• Digital system testing and testable designs
• Tools and languages:- Verilog, Xilinx Vivado, Electric (layout and schematic design), C, Python