HEMANTH VARMA PUTTA
Summary
Hardworking and reliable PD Engineer with strong ability in Synthesis, LEC, STA/Timing closure, perl and TCL. Timing checks and analyzing design issues and fixes. Highly organized, proactive and punctual with team-oriented mentality.
Overview
2
2
years of professional experience
Work History
ASSOCIATE I - ENGINEER
CAPGEMINI
08.2022 - Current
- Clock Gating adding ICG’s if the clock needs to be gated.
- Optimized memory macro's through advanced techniques such as bit swapping and word line mirroring.
- Performed LEC check and tried to enhance and implement the corrections required using EOC.
- Performed Scan insertion to add scan flops in order to test the flops during DFT.
- Physical Design Flow (Data preparation, Floorplan, powerplan, placement, CTS, Routing).
- Performed timing closure analysis, optimization and verification of chip designs.
- Manual Data, Clock, Transition Fixes.
- Manual Setup Fixes and Hold Fixes.
- Debugging issues as minimum pulse width issues.
- Cross talk Noise & Delay Fixes.
- Creating UPF File according to design.
- Creating Multiple Power Domains of multiple voltage areas.
- Inserting Low power cells like Level shifters, isolation cells, Retention cells.
- Performed low power synthesis and VCLP checks on synthesis netlist
- Created floor plans with high utilization of area, power and performance goals.
- Optimized synthesis results to meet timing constraints and power budgets.
- Utilized scripting languages such as Tcl and Tk, Perl, Python to automate the flow of tasks in the physical design process.
- Performed static timing analysis on blocks and full-chip level using PrimeTime or similar STA tools.
Education
B.TECH - ELECTRONICS AND COMMUNICATION ENGINEERING
GITAM UNIVERSITY
VISAKHAPATNAM04-2022
Skills
- Placement Optimization
- Sanity checks
- Analyzing Timing reports
- Debugging Setup, Hold and DRV’s issues
- PERL
- TCL
- Design Compiler
Capgemini | Intern
Interned at Capgemini Engineering in Physical Design(VLSI).
Tools
- Design Compiler & Fusion Compiler.
- Prime time(STA) & ICC2.
Timeline
ASSOCIATE I - ENGINEER
CAPGEMINI
08.2022 - Current
B.TECH - ELECTRONICS AND COMMUNICATION ENGINEERING
GITAM UNIVERSITY
Similar Profiles
Abdoul-rahim DombaAbdoul-rahim Domba
Ingénieur d'études et de recherche at CapgeminiIngénieur d'études et de recherche at Capgemini
Bélinda BONACINABélinda BONACINA
Document Management, quality and configuration at CAPGEMINIDocument Management, quality and configuration at CAPGEMINI
Namrata DwivediNamrata Dwivedi
Front End Developer at CapgeminiFront End Developer at Capgemini