Keerthi SP

Tapedout 65nm SCBM34XX version 2.0 SOC & 55nm GPS transceiver SCGN25XX.

Leading a team of 4 for SCBM34XX tapeout.

• SCBM34XX Top Floorplan,DRC and LVS - Placement of Analog (baseband + RF),Digital TOP integration & Area IO(Bump , ESD placement and routings)
• SCGN25XX chip Floorplan,DRC and LVS - Placement of Analog (baseband + RF),Digital TOP integration & Area IO with WLCSP package.
• Experience working as a design lead in a team environment on mixed-signal ICs and integrating SerDes, DDR PHY or analog mixed-signal chip.
• Bump and Ball placement for FCBGA package , by planning first-cut board layout & with first-cut ball to bump routings. Involved in the routing of high-speed signal routings(DDR,PCIE,CPRI) & RF routing.
• Designed FCBGA package for SCBM34XX in orcad pcb. Various scripts done in skill and shell for netlisting and automatic bump and ball placement in pcb.
• Designed the complex evaluation board for the SCBM34XX in orcad capture.(Power supply schemes,Peripheral options,rf and high speed circuits).
• Bring up and evaluation of RF system boards.(RX Noise figure measurements and debug, PA power and gain adjustment).
• Coordinated with various vendors like package manufacturer,assembly.

Tapedout 65nm SCBMXXXX SoC

• SCBMXXXX SoC Top Floorplan, DRC and LVS - Placement of Analog (baseband + RF), Digital TOP integration & Area IO(Bump and ESD placement and routings).
• Worked on DDR PHY Floorplan, LVS, DRC and integration with DDR digital and DDRPLL.
• DDRPLL : Various block in ddrpll like 64 phase mux , ldo, vco and Delay lock loops, which is one of the complex circuit designed. The placement and routing for this block to match 64 pahses took some real work.
• Use QRC extraction to analyze and reduce noisy/sensitive coupling.
• Planning and routings of DDR address and data lines from block to bumps.
• Worked on High speed circuits blocks like PCIE and CPRI.
• Planning and routings of various sensitive lines. (LO, Mixer routings, LNA Input, PA output etc).
• Done chip top placement of reference clock buffer and routings.
• Guard rings for individual blocks and analog to digital separation.
• ESD layout optimization and placement in top.
• Planning and designing of FCCSP package for SCBMXXXX.
• A 16 layer complex PCB evaluation board design and layout for SCBMXXXX.

• Cleaned full chip LVS, DRC & handled various signal and power routings.
• Used calibre to measure p2p resistance for power and esd planning.
• Able to work high frequency RF block(6G 6G LNA,PA and MIxer).
• Worked on various base band blocks like filter,ADC,DAC,Bandgap.
• Implemented automatic placement and routing of current mirror circuits with skill and shell.
• With tcl/wish wrote scripts for DRC/LVS result viewers, metal-density/EM violation highlights & various other helpful utilities for the team.