Summary
Overview
Work History
Education
Skills
Languages
Websites
Timeline
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Jayashree M M

Jayashree M M

Bengaluru

Summary

Experienced FPGA Engineer with 5+ years of designing and verifying FPGA systems. Skilled in developing complex FPGA designs, synthesizing and verifying the designs. Proficient in programming Verilog, VHDL for FPGA programming. Highly-motivated employee with desire to take on new challenges. Strong worth ethic, adaptability, exceptional interpersonal skills and quickly mastering new skills.

Overview

6
6
years of professional experience

Work History

FPGA Design Engineer

Centum T&S
Bengaluru
03.2022 - Current
  • Strong Knowledge on FPGA Architecture and FPGA Design Flow.
  • Knowledge on Programming Languages - VHDL, Verilog, System Verilog
  • Experience in DO-254 process oriented projects
  • Designed and developed FPGA based IP Cores for various applications.
  • Developed test benches to validate the functionality of designed FPGA designs.
  • Analyzed and debugged existing FPGA designs, including Verilog code, simulation results and timing constraints.
  • Performed synthesis and place and route operations on Xilinx Virtex-7 FPGAs using Xilinx ISE Design Suite 14.4.
  • Experience in using Tolls from different FPGA vendors like Lattice, Microsemi.
  • Optimized existing RTL code to meet timing constraints while maintaining functionality of the design.
  • Provided guidance to junior engineers on best practices for designing with FPGAs.
  • Analyzed customer requirements, identified design issues, and proposed solutions.
  • Documentation as per the DO254 process.

FPGA Engineer

Bharat Electronics Ltd
Bengaluru
07.2017 - 03.2022
  • Experienced with working in Xilinx Zynq SoCs for Time distribution over NTP/PTP (Stratum-0).
  • Knowledge on GPS/GLONASS/IRNSS based Receivers.
  • Disciplining of Rubidium Clock for Holdover requirement in Time Servers and to provide 1PPS/10MHz outputs to the systems in the network.
  • Development of MMI (Display and Alpha-numeric Keypad) for the product. Integration RTL design/Block design in Xilinx Vivado .

Education

Bachelors of Engineering - Electrical, Electronics And Communications Engineering

Siddaganga Institute of Technology
Tumkur
07.2017

Skills

  • Project Coordination
  • Product Development
  • Requirements Analysis
  • Microsoft Office
  • Version Control using SVN, Git
  • Team Player

Languages

English
First Language
French
Beginner (A1)
A1

Timeline

FPGA Design Engineer

Centum T&S
03.2022 - Current

FPGA Engineer

Bharat Electronics Ltd
07.2017 - 03.2022

Bachelors of Engineering - Electrical, Electronics And Communications Engineering

Siddaganga Institute of Technology

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Jayashree M M