Jeby Jose

Currently working as Verification architect at AITC team of Intel technologies, delivering many Mixed Signal IP's and Test chips. Was lucky enough to secure dream job in VLSI during the great recession time period (2008 to 2009), my career starts just after securing a high Score in master degree in VLSI Design engineering from one of the reputed institutions. Though good at Coding when chances are given my choice was to follow my passions in Art of validations. One has to think limitlessly in the infante space of possibilities to prove or disprove a Design, this challenging nature of the validation jobs and its problem-solving requirements made me passionate about this job. Throughout these 14 years of Carer was part of various validations teams across the industries with Cutting edge technologies like Routers, OMAP, Modem, DSP, Processors, High speed interfaces, Memories, Driver less car, Multi -pixel Phone, server & client Devices. Also, could work for SoCs, Subsystems, Test Chips and IP's. Passion towards uncompromised Quality and validations helps keeping me energetic throughout the day even after spending hours in, various day to day challenges and problem-solving activities.

• M-tech in VLSI -Design with a higher score of 89.5 %
• 945 All India rank (97.3 percentile) in GATE -2007
• Two Bachelor Degrees (BSc Math and Engineering)
• Associated Membership in Institute of Electronics and Telecommunication Engineering (IETE)
• Secured 40 performance Awards and recognitions
• 2 Certifications on Design Security analyzing
• Continues Outstanding performer ratings for last 4 cycles
• Inventions in High-rate detection capable ECC (4 bits)
• 4 paper presentation including Snug
• Developed Scalable and reusable SPID/DFI based TB which will supports multiple projects, and supports various Methodologies simultaneously. (UVM, OVM, XVM, Saola)
• Given many trainings across the organization on SV, UVM, and SVA
• Given Tech talks on various quality initiatives
• Automations of Converge and Complex cross coverage coding using Python
• Innovative test plan creation which captures the Complete spec and corner cases in machine readable format
• Pioneered Complete Test Chip from scratch by setting up a very cost-effective team and successfully delivered many bugs free Test Chips data bases to foundry in a short duration.
• Automation of Test chip TB development form Pin list and connectivity list spec
• Automation in Post silicon Collateral generation form Pre-silicon tests
• Successfully delivered MDFI (Die to Die) IP using custom made BFMs with Zero Silicon Bug

• Good interpersonal communication skills.
• Innovations in daily activates
• Strong coding skills.
• Sharp grasping power
• Problem solving and trouble-shooting.
• Good RTL debugging skill.
• Good analytical and logical reasoning skills .