JYOTHIRMAYI KANDUKURI
Bangalore
Summary
Highly logical and problem-solving oriented professional with over 6 years of experience in ASIC RTL Design within the Image Processing Unit Team in SoCs. Expertise in RTL design using Hardware Descriptive Languages (HDL) such as Verilog and System Verilog. Solid foundation in scripting languages like SHELL and PERL for effective automation implementation. Well-versed in Design Checks based EDA Tools like Spyglass LINT and Spyglass CDC of Synopsys, as well as High-Level Synthesis (HLS) based Stratus Tool of Cadence using System C language. Strong debugging skills to efficiently identify design and verification issues, complemented by experience with VCS and Verdi. Goal is to leverage skills and knowledge to contribute to organizational success while achieving personal ambitions.
Overview
7
7
years of professional experience
Work History
IP LOGIC DESIGN ENGINEER
INTEL TECHNOLOGY INDIA PVT LTD
02.2018 - Current
- Fairly good understanding of Image processing pipeline and was responsible for developing one of the Image processing blocks called AutoFocus Pixel Extraction Block responsible for extracting Auto Focus Pixels from the Pixel streams
- I was also partially involved in another Image processing function called Blend that is used to blend pixels from the current image, the spatially filtered current image, and the previously cleaned reference image, based on the Recursive Similarity
- Major experience in providing debug support and solutions to various IP blocks in Image Processing Unit (IPU) of Intel SoCs
- Developed unit level RTL designs using Verilog and System Verilog including blocks to support Timestamp and other Design for Debug Solutions
- SoC (System On Chip) level Debug logic RTL Integration across various IPs to provide debuggability of the design which later becomes a useful tool for the designers to identify various bugs at Post Si level
- Extensive Experience in integration and verification of VISA(Visualization of Internal Signals Architecture) a mux based infrastructure to view important design signals at SoC pin level and trace aggregator
- Good knowledge of APB, ATB and DTF(Debug Trace Fabric) Interfaces for trace and debug
- Developed and delivered DFD(Design for Debug)subsystem, a subIP that provides various debug and trace solutions with all necessary RTL quality checks like CDC, lint and collaborated with multiple designers for its integration based on floor plan
- Provided Post Si debug support for enabling VISA and Trace in IPU IP level by providing Programming sequence
- Micro Architecture Specification Documentation and ability to analyze Verification Scope for a given design
- Waveform, assertions, test sequence and Coverage reviews with verification team
- Developed Shell and PERL based scripts to automate the generation of various RTL and Verification related collaterals
- Excellent coordination with peers in execution and knowledge sharing to other team members required for project implementation
- Good communication skills and pro activeness to solve issues, thereby providing essential cross team collaboration support especially Functional Design, Verif and Post Si Team
- Have received multiple recognitions for hardwork, dedication, customer orientation, innovation, high performance and on time delivery
- Exhibited Good Flexibility as individual performer as well as a Team Member
Education
B. Tech - Electrical & Electronics Engineering
SRM University
Kattankulathur, Chennai05.2017
H.S.C -
Fatima Matriculation
04.2006
S.S.C -
Dr.D.Y.Patil Public School
03.2004
Skills
- VLSI Design
- Verification
- Synchronous FIFO
- Booth Multiplier Algorithm
- QUESTA SIM 105
- VIVADO 20163
- Spyglass LINT
- Spyglass CDC
- VC LINT
- Stratus
- VERDI
- DVE
- Verilog
- System Verilog
- Shell
- Basic PERL
Accomplishments
Received Divisional Recognition Award for area saving and integration smoothening strategy
Languages
Telugu
English
Hindi
Tamil
Marathi
Kannada
Extra-Curricular Activities
Assisted as a volunteer in organizing many Seminars of NIPM in Pune. Head of the Internal Publicity Committee in College Organizing Team for the Technical Fest “AARUUSH” in SRM UNIVERSITY. Participated in many Elocution and Debate Competitions. Organized social activities in rural areas on behalf of some NGOs. Coordinated Pondicherry University MSW Students for their Field Work in Social Service Project.
Personal Information
- Date of Birth: 03/09/90
- Gender: Female
- Marital Status: Married
Achievementsandawards
- Was a School Pupil Leader of the School
- Won a Silver Medal in Maharashtra Talent Search Examination during Secondary School.
- Topped my GROUP (MPCBi) and stood third in Higher Secondary School
- Was awarded with a scholarship of Rs. 1 Lakh in the SRM College for my academic performance.
Hobbies and Interests
- Reading Books
- Dancing
- Cooking
- Acting
Additional Information
Cross collaboration
Timeline
IP LOGIC DESIGN ENGINEER
INTEL TECHNOLOGY INDIA PVT LTD
02.2018 - Current
H.S.C -
Fatima Matriculation
S.S.C -
Dr.D.Y.Patil Public School
B. Tech - Electrical & Electronics Engineering
SRM University
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