JYOTIRMAYA JYOTI
Summary
Focused Hardware Engineer with an impressive track record in collaborative, cross-functional teamwork within high-pressure environments. Keen to take on challenging new roles harnessing interpersonal skills, collaboration, and problem-solving. Driven to deliver high-quality and consistent results.
Overview
1
1
year of professional experience
1
1
Certification
Work history
Hardware Engineer
Samsung Semiconductor
Bangalore
2022.08 - Current
- Working in NVMe IPDV team, Responsible for RAL Testing and Module Level Testing with experience in creating Testplans, Testcases, and Checkers.
- Co-work with the Design team in Debugging, Functional Coverage / Code Coverage closure.
- Utilized basic scripting skills to help develop Automated Regression Framework which resulted in significantly reduced redundant efforts and improved team efficiency.
- Basic exposure to Clock Gating Verification.
Education
M.Tech Micro - Electronics & VLSI
Indian Institute of Technology
2022
B.Tech - Electrical Engineering
Institute Of Engineering & Management
2019
Skills
- Programming - Verilog, TCL, System Verilog, UVM
- Protocols - AXI, NVMe
- EDA Tools - Xcelium-Simvision, JasperGold, vManager, Lumerical- Ansys, Cadence- Virtuoso, NgSpice, Mentor Graphics- Eldo, Xilinx ISE, ASITIC
- Analog Domain - Analog IC Design, RFIC Design and Mixed-Signal Design
- Digital Domain - Introduction to VLSI Design and Digital IC Design
- Devices and Technology - Semiconductor Device Modelling, VLSI Technology, Nanophotonics, and Nano Electronics
Academic Projects
- Non-reciprocal System Design & RF Filter Synthesis based on Passively Coupled N-Path Filters
Realized a High-Q N-Path inductor-less filter tunable by the clock frequency. Achieved a 36dB Return loss and 1.9dB Insertion loss.
- Design of a 2.4 GHz Low Noise Amplifier
Implemented Common Source LNA with Inductive degeneration. The circuit is optimized for achieving High Gain, Low NF, and Input Return Loss & verified the linearity of the circuit.
- Verification of AXI Memory
Implemented Write and Read Channel, Developed corresponding Verification Environment
Certification
- Maven Silicon - STA, System Verilog, UVM
- UDEMY - Physical Design Flow, Clock Tree Synthesis, Signal Integrity
Timeline
Hardware Engineer
Samsung Semiconductor
2022.08 - Current
M.Tech Micro - Electronics & VLSI
Indian Institute of Technology
B.Tech - Electrical Engineering
Institute Of Engineering & Management