Kalyani Gaikwad
Pune,
Summary
Dynamic Graphics Hardware Engineer/Verification Engineer with 7+ years of experience in GPU verification domain, proficient in developing and executing comprehensive verification plans, methodologies and test benches to ensure high quality designs with proven ability to identify and resolve complex verification issues. Looking forward to leverage my knowledge into new challenging roles.
Overview
11
11
years of professional experience
Work History
Graphics Hardware Enginner/Verification Engineer
Intel Technology
05.2018 - Current
- Verification plan development, working with design engineers to resolve the specifications of complex components, and creating verification specifications accordingly.
- Developed comprehensive test plans.
- Drive and adopt new verification methodologies, tools and flows to improve efficiency and effectiveness.
- Unit Level Verification: Owned a unit level TB execution, feature validation in the unit by enhancing env/TB, developing required verification/testbench components such as BFMS, checkers, running functional simulations and debugging failures, coverage coding, analysis and creating testcases to ensure maximum coverage.
- Cluster Level Verification: Bringing up cluster testbench/env for any new project based on the requirements including integration of different RTL design units, resolving connectivity/x-prop issues, extending existing verification environments to improve the quality of verification, developing required verification/testbench components such as BFMS, checkers etc. to support new feature validation, running functional simulations and debugging failures, coverage closure.
- Developed verification IP which can be reused at different levels of verification.
- Architect and develop verification environment and testbench components such as BFMs and checkers etc. along with uvm components such as monitor, driver, scoreboards.
- Updating existing uvm environment/components such as agents, sequences, scoreboards etc.
- Developed/modified perl scripts to automate tasks involved in verification process, infrastructural work including developing scripts for efficiency and quality improvements.
- Coverage driven verification: Coverage coding, functional and code coverage analysis to ensure thorough testing and achieving desired coverage goals.
- Debugged and resolved critical corner case scenarios.
- Worked collaboratively with cross functional teams including design engineers and other team members to ensure comprehensive verification and to understand design intent and implementation details.
- Maintained detailed documentation including verification processes, TB/env details, flow diagrams, debug details, coverage scenarios etc.
- Demonstrated ability to work independently as well as in a interdisciplinary team.
Technical Intern
Intel Technology
07.2017 - 04.2018
- Unit level Verification of Graphics Card Texture Sampler.
- Understanding features to be verified.
- Engaged in verification environment architecture and methodology development.
- Verification of architectural features of the designs by developing verification specs, developing and executing test plans, developing or modifying test content, running functional simulations and debugging failures.
- Coverage driven verification: Coverage coding, analysis and achieving required functional coverage.
- Creating directed and random unit level verification tests.
- Tweaking test cases in perl to verify and cover desired scenarios.
Associate Software Engineer
Tech Mahindra
06.2014 - 07.2016
- Worked on Telecommunication project for AT &T on IBM Mainframe platform and Quality Centre.
- Experience includes first 6-7 months training followed by Manual Testing using JCL on IBM OS/390 Mainframes under the OS/390 Operating system and execution and debugging of test cases using QC.
Education
Mtech VLSI Design -
Vellore Institute of Technology
Vellore01-2018
BE(E&TC) -
Imperial College of Engineering
Pune01-2014
Skills
- Foundational UVM Knowledge
- Experienced in System Verilog and Verilog
- Perl Scripting
- Debugging Techniques
- Coverage Driven Verification
- Assertion Based Verification
- Constraint Randomization
- Documentation
Timeline
Graphics Hardware Enginner/Verification Engineer
Intel Technology
05.2018 - Current
Technical Intern
Intel Technology
07.2017 - 04.2018
Associate Software Engineer
Tech Mahindra
06.2014 - 07.2016
Mtech VLSI Design -
Vellore Institute of Technology
BE(E&TC) -
Imperial College of Engineering
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