Experienced Analog Design & Verification Engineer skilled in validating and designing high-performance analog/mixed-signal circuits using tools like Cadence and Spectre. Proficient in schematic to corner analysis, and mixed-signal verification with a focus on reliability and silicon accuracy..
Characterization & Modeling of CDS-PGA for CMOS image Sensor
Designed and verified Programmable Gain Amplifier (PGA), for higher dynamic range in CMOS image sensor, using switched capacitor amplifier in 180 nm technology on Cadence Virtuoso ADE and modeled it in Verilog-A. Further, integrated CDS (Correlated Double sampling) technique to the PGA to remove offset error.
Two Stage CMOS op-amp(7T-OTA) for analog I/O buffer
Designed and verified two stage CMOS Op-Amp for given specifications in 180 nm technology on Cadence Virtuoso ADE.
Did prelay & postlay verifivation of various analog blocks like Voltage Reference ,Current Reference, LVDS ,Class-AB Power amplifier, level shifter,7T-OTACDS-PGA by performing AC,DC ,transient and PVT across corner analysis on Cadence Virtuosos ADE to verify parameters like ICMR, loop gain, phase margin,UGB, Slew rate,CMRR,PSRR etc.
Asynchronous FIFO using Verilog -HDL, 10/2023- 12/2024
Designed an asynchronous FIFO memory using memory, write pointer logic, read pointer logic, synchronizer, gray counter etc. Implemented on RTL level using Verilog HDL on Xilinx ISE and verified its functionality.