KETAN THAKUR
Shimla
Summary
Dedicated and adaptable professional with a proactive attitude and the ability to learn quickly. As a verification engineer, I have experience in various aspects of verification, including validation, GLS (Gate-Level Simulation), and formal verification. I possess a strong work ethic and effective communication skills, eager to contribute to a dynamic team and support organizational goals.
Overview
4
4
years of professional experience
Work History
Formal Verification Engineer
Excelmax Technology
Banglore
03.2024 - Current
- Worked as a Formal Verification Engineer specializing in NVMe memory controllers and validation utilizing JasperGold tool
- Implemented validation planning from unit takeover to formal sign off.
- Implemented assertions, covers, and coverage sign off for complex control path units in FPV.
Design Verification Engineer
Tech Mahindra
Banglore
09.2020 - 02.2024
- Ensured pre-silicon validation of hardware engineering for graphics.
- Running coverage regressions on GT model and reporting the results to clients.
- Resolved regressions by debugging and fixing failed tests.
- Oversaw synchronization of passing tests in the ATS queue and produced comprehensive Excel reports through regression analysis.
- Built GLS environment, executed zero delay simulation and conducted debugging
- Developed test cases for the I3C protocol
Education
Master of Science - VLSI
Chandigarh University
Punjab08-2019
Bachelor of Technology - Electronics And Communication Engineering
Kurukshetra University
Kurukshetra08-2015
Skills
- ASIC front-end Design and verification
- Verilog,System Verilog,UVM\
- Gate Level Simulation
- Formal Verification
Languages
Hindi
First Language
English
Upper Intermediate (B2)
B2
Timeline
Formal Verification Engineer
Excelmax Technology
03.2024 - Current
Design Verification Engineer
Tech Mahindra
09.2020 - 02.2024
Master of Science - VLSI
Chandigarh University
Bachelor of Technology - Electronics And Communication Engineering
Kurukshetra University
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