Design Verification Engineer
Velzonn Global Solutions Pvt Ltd
01.2021 - Current
- Understood the architecture and logic design of AES and ShA-3.
- Designed the RTL module of AES and SHA-3 using Verilog.
- Verified the RTL module of AES and SHA-3 using Verilog.
- Prepared verification plan to implement the VIP.
- Developed generic Verification environment required for AXI Master and Slave in the AXI BUS transaction.
- Written test cases to cover different scenarios of protocol.
- Verified the RTL module using System Verilog
- Generated functional and code coverage for the RTL verification sign-off.
- Understood the AMBA APB specification and was involved in development of Test Plan.
- Development of components like APB sequence item, driver.
- Validating APB Master using APB Slave model.
- Responsible for writing test cases to cover different scenarios.
- Written test cases to cover all functional features