Summary
Overview
Work History
Education
Skills
Languages
Timeline
Generic

K ARUNA

Summary

  • Design Verification Engineer with 3 years of experience.
  • Currently working in Velzonn Solutions Pvt Ltd Verification Engineer.
  • Good knowledge on,Verilog, System Verilog and UVM methodology
  • Strong hold serial communication and bus protocols like AXI , APB , SPI, I2C and UART.

Overview

18
18
years of professional experience

Work History

Design Verification Engineer

Velzonn Global Solutions Pvt Ltd
01.2021 - Current
  • Understood the architecture and logic design of AES and ShA-3.
  • Designed the RTL module of AES and SHA-3 using Verilog.
  • Verified the RTL module of AES and SHA-3 using Verilog.
  • Prepared verification plan to implement the VIP.
  • Developed generic Verification environment required for AXI Master and Slave in the AXI BUS transaction.
  • Written test cases to cover different scenarios of protocol.
  • Verified the RTL module using System Verilog
  • Generated functional and code coverage for the RTL verification sign-off.
  • Understood the AMBA APB specification and was involved in development of Test Plan.
  • Development of components like APB sequence item, driver.
  • Validating APB Master using APB Slave model.
  • Responsible for writing test cases to cover different scenarios.
  • Written test cases to cover all functional features

Assistant Professor

UG And PG Institutions
06.2006 - 02.2017
  • An Electronics enthusiast with 11 years of experience in guiding, motivating and Inculcating the knowledge for the aspirants in Electronic Science.

Education

Master of Science - Electronic Science

Bangalore University
Bengaluru, India
06.2006

Skills

  • Digital System Design (DSD)
  • VHDL/Verilog modelling
  • RTL design and verification
  • Gate Level Simulation (GLS)
  • RTL Coding and Synthesis
  • Test Benches
  • VLSI Design EDA Tools
  • ASIC design
  • System Verilog (SV)
  • Universal Verification Methodology (UVM)
  • C/C programming
  • Microprocessors, Microcontrollers
  • Analog Electronics

Languages

English
Kannada
Telugu
Tamil
Hindi

Timeline

Design Verification Engineer

Velzonn Global Solutions Pvt Ltd
01.2021 - Current

Assistant Professor

UG And PG Institutions
06.2006 - 02.2017

Master of Science - Electronic Science

Bangalore University
K ARUNA