Likhil Kurella
Jalli Kommara
Summary
Highly-motivated employee and a future student with desire to take on new challenges. Strong work ethic, adaptability, and exceptional interpersonal skills. Adept at working effectively unsupervised and quickly mastering new skills.
Overview
2
2
years of professional experience
1
1
Certification
Work History
Design Verification Engineer
COREEL TECHNOLOGIES
BANGALORE
08.2022 - Current
- Provided technical support for customer applications by analyzing logs generated from emulation platforms.
- Participated actively in cross-functional meetings with Designers providing feedback on functionality testing of design.
- Performed code coverage analysis to ensure all functionality was tested in the design verification process with numerous testcases.
- Collaborated closely with designers to identify bugs early in the development cycle through debugging techniques such as waveform viewing, logic analyzers or printing report files.
- Developed test plans and strategies for verifying design integrity of integrated circuits at module level.
- Documented test bench design for both the project which explains the complete verification environment used throughout the project lifecycle to ensure consistency for test bench.
- Participated in reviews of test plans, results, and bug reports with peers and customers.
- Implemented directed tests using SystemVerilog language constructs and used .tcl and python scripts to make sure the flow of verifying a Test Bench was proper.
- Utilized System verilog methodology for building verification environment components like drivers, monitors.
- Evaluated new technologies related to Verification Methodologies and Toolsets that could benefit design teams.
- Identified areas where performance can be improved through optimization techniques.
- Analyzed and debugged complex RTL code using simulation tools such as Modelsim and Xilinx Vivado
- Mentored junior engineers in proper use of languages, toolsets, methodologies, processes, and coding standards.
- Assisted in developing automation scripts with TCL and python to improve efficiency of the verification flow.
- Sketched outline designs and used microsoft VISIO to create detailed designs.
- projects worked on were ADE_TVCSU and LRDE_COLOR.
- Worked on different FPGA's for COLOR project where in one board named TWFG, different ethernet packets were generated, depacketized and sent to separate controllers based on packet type and device type and sent out through AXI stream interface controller to out of the FPGA which connects to a software developed module.
- Created separate verification environments which includes test plans and test reports for different types of packet generations in ethernet stack for both cards and later combined all packet generations in a single verification environment for creating a perfect verification test bench.
- For TVCSU, verified different boards like FCC, ATS and ARINC_CARD.
Education
CBSE (Central Board) -
Bharathiya Vidhya Bhavans Residential Public School
01.2016
B. Tech in Electronics and Communicational Engineering -
Sastra Deemed To Be University
Intermediate (BIEAP) -
Tirumala Junior Kalashala
Skills
- programming language like C, C, Verilog, System Verilog with scripting language TCL
- Assertion-based verification
- Functional Coverage
- Digital circuit knowledge
- Formal verification techniques
- Verification planning
- Testbench development
- Gate-level simulations
- SystemVerilog expertise
- Design Verification
- Communication Skills
- Electrical Engineering Standards
- RTL design understanding
Certification
- Career Skills certified by TCS-ION Apr 2020
- Career Edge-Knockdown the Lockdown certified by TCSION Jun 2020.
- C, C++ Training completion by Spoken Tutorial Project by IIT Bombay
- First Step Korean conducted by Yonsei University, Korea (foreign language)
Accomplishments
- Secured Elite Certificate in 'NPTEL Employment Communication'
- Zonal Level Chess Player
Activities
- Member of an event organizing team from 1st year
- Participated in college cultural events
- Organized many events through INFRA team with fellow mates
- Participated in Science fare events like DAKSH which is one of the biggest scientific fest in India
Hobbies and Interests
- Playing badminton
- Streaming YouTube
- Learning things and technologies
Languages
Telugu
First Language
English
Advanced (C1)
C1
Tamil
Upper Intermediate (B2)
B2
Hindi
Intermediate (B1)
B1
kannada
Beginner (A1)
A1
Timeline
Design Verification Engineer
COREEL TECHNOLOGIES
08.2022 - Current
CBSE (Central Board) -
Bharathiya Vidhya Bhavans Residential Public School
B. Tech in Electronics and Communicational Engineering -
Sastra Deemed To Be University
Intermediate (BIEAP) -
Tirumala Junior Kalashala
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