Keyurkumar Patel

To secure a challenging position where I can effectively contribute my skills as a professional.

I have a total of 7+ years of experience.

Staff Engineer (L3), Synopsys (IND) Pvt Ltd, Aug 2024 - Current Working.

Senior Design Verification Engineer, April 2023 - July 2024, Tech Mahindra Cerium Pvt. Ltd., Ahmedabad. Client: Intel.

Senior Design Verification Engineer, Design Verification Engineer, EINFOCHIPS - An Arrow Company, Ahmedabad. Clients: Intel, Alif Semiconductor, and Infinera. April 2022 - Dec 2023. January 2020 - March 2022.

Design Verification Engineer. June 2018 - December 2019. Perfect VIPs Pvt Ltd, Ahmedabad. Internal Project: APB and DDR4 Controller. Internship at Indicus Technology, Ahmedabad. Training for SV/UVM and Verilog HDL language. Aug 2017 – May 2018

• Elite level certificate in Indicus Technology certificate course 'SV/UVM'.
• Beginner level taken training for Formal Verification given by E-Infochips (An Arrow).

Published paper 'Optimization 8-Bit ALU using Hybrid LUT/MUX FPGA Design using Verilog HDL'

Optimization 8-Bit ALU this is my MTech Project and also worked on Thesis.

Working with Ethernet (25G, 10G, and 2.5G). First understanding of protocol and test flow. Then working with regression, debugging test cases, and another scenario. Developed code coverage and function coverage. Updated all checkers as per specification.

Intel, IP (June 2023 to Feb 2024), Ramp up on block Design and Testbench structure., Start working on bring up testcases for TX layer., Update existing testbench as per new features requirement., Test requirements gathering, development, debugging and submitting in regression., Testcases analysis and failure debugging.

Ethernet internal Project (Black Box Verification) (Dec 2022), Developed the test bench setup for 1 Giga bit Ethernet MAC internal Project., Tx and Rx packets compare frame packets in scoreboard., Developed all environment structure., Wrote all component classes.

Infinera, OTN (Aug 2022 to Nov 2022), Understood design specification for OTN project., Regression testcases analysis and failure debugging., There FPGA has multiple blocks like, FEC, OTN, Ethernet and XTPF verify performance., Debugging failure in test, filing Bug in RTL.

Alif Semiconductor, SOC (May 2021 to July 2022), Start working on SOC base project., 7 Processor have., Worked on VBAT processor., It’s for voltage battery processor and worked on interrupt signals., Developed testcases for Vbat, Timer0, 1, 2, 3 and Timer 4 for Power on-off condition check, Same scenario created for multi time power on-off., Wrote function coverage for all wake-up events interrupts signals., Got 100% coverage report., Regression testcases analysis and debugging for SOC frailer testcase.

Intel, PCIe 4.0 Express (June 2020 to Dec 2020), Worked on PCIe 4.0 Gen IP system level as shadow engineer., Responsible to run all regression testcases and report to manager about failure testcase., Worked on negative exiting testcase and updated as per new build RTL., Updated another testcases as per future testcase list.

DDR4 Internal Project (Black Box Verification) (Feb 2019 to Nov 2019), DDR4 Controller, Start Worked with internal DDR4 project., Understood DDR4 standard JEDEC specification., No have design but Created components like transaction class, interface, monitor and scoreboard w.r.t DDR4 specification., Wrote monitor class for all CMD and check timing parameter w.r.t design specification., Wrote scoreboard for check all CMD activity.

AMBA Bus Protocol (Black Box Verification) (Aug 2018 to Jan 2019), APB, Develop APB RTL design in System Verilog., Verified APB design in UVM testbench, Debugged and developed test-cases for verification of APB protocol.

ALU, 8-Bit ALU Design (Aug 2017 to May 2018), Wrote code in Verilog., Design in 8-bit ALU and covered adder, sub, multi, division, and, or and not operation in through using this design., Verified this design using UVM methodology.

Verilog, System Verilog, UVM, Formal Verification Knowledge, Synopsys VCS/VCF, Cadence Xcelium, Mentor Questa sim, AMBA APB, AHB, AXI-3/4, I2C, Python, TCL, C, C++