Kushal S
Bengaluru
Summary
VLSI design expert with extensive experience in analog layout design at Takshila VLSI. Skilled in Layout designing , with a proven ability to solve complex problems. Enhanced design processes through research on emerging technologies, showcasing a dedication to innovation in integrated circuit design.
Overview
1
1
year of professional experience
Work History
Analog Layout Design Trainee
Takshila VLSI
Bengaluru
05.2025 - Current
- Currently working as an Analog Layout Design Intern at Takshila VLSI, where I am gaining practical experience in the design, layout, and verification of analog integrated circuits following industry-standard methodologies.
- Conducted research on emerging technologies to enhance design processes.
Intern
Internshala
Bengaluru
09.2024 - 11.2025
- Completed an internship in VLSI Design through Internshala Training, covering topics such as HDL coding, combinational and sequential circuit design, finite state machines, and FPGA-based system design. Gained a solid foundation in VLSI concepts and digital design principles.
Education
B.E. - Electrical & Electronics Engineering
BMS College of Engineering
Bangalore05-2025
Skills
- Cadence Virtuoso
- Xilinx Vivado
- Proteus 8 Professional and EDAPLAYGROUND
- ModelSim for Verilog simulation
- MATLAB and Simulink modeling
- Python programming and scripting
- Arduino IDE integration
Projects
1. Fire Protection Robot
Duration: 3 Months
- Built a robot to detect and extinguish fires using temperature and flame sensors.
- Integrated an automated extinguisher system for fire suppression in diverse environments.
2. 8-bit ALU Design (Xilinx Vivado)
Duration: 2 Months
- Designed an 8-bit ALU capable of performing eight operations using Verilog HDL.
- Simulated and implemented the design using Xilinx Vivado.
3. IoT-Based Anti-Vehicle Theft System
Duration: 3 Months
- Developed a system to track live vehicle location and send alerts for theft or accidents.
- Used GPS, GSM, and the Blynk app for real-time monitoring.
Extracurricular Activities
Logistic Head BMSCE ISRC (Institute of social responsibility cell) – Led as a coordinator initiatives for events.
Logistics and media head EEEA(Electrical and electronics engineering association) – Executed successful technical events.
Timeline
Analog Layout Design Trainee
Takshila VLSI
05.2025 - Current
Intern
Internshala
09.2024 - 11.2025
B.E. - Electrical & Electronics Engineering
BMS College of Engineering
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