SIDDESH PATIL

Summary

Recent engineering graduate with one year of hands-on experience as a Mixed Signal Layout Engineering Intern, specializing in analog and digital circuit layout implementation for real-world projects. Skilled in applying academic knowledge to create efficient and reliable integrated circuit designs. Eager to expand expertise in Design Verification (DV) and Physical Design (PD), with a strong commitment to learning and contributing to innovative chip design solutions. Ready to leverage foundational skills and adaptability to excel in diverse, integrated circuit design roles.

Overview

year of professional experience

Work History

Analog Mixed Signal Layout Engineer

Microchip Technology India Pvt Ltd

Bangalore

08.2024 - Current

Having 1 year of experience in Analog, Mixed Signal Layout Design.
Worked on one of the blocks of SERDES (128 Gbps) in 3nm (TSMC)
Experience in 3nm(TSMC) and 16nm (TSMC) technology nodes.
Developed one of blocks of PLL from scratch(floorplan to DRC & LVS)
Created and modified Standard Cells of various types in 16nm (TSMC).

Education

MTech - VLSI Design

Vellore Institute of Technology

Vellore

08-2025

B.E. - Electronics Engineering

Ramrao Adik Institute of Technology

Navi Mumbai

05-2022

HSC - Science

V. G. Vaze Kelkar College of Science

Mumbai

05-2018

SSC -

I.E.S Secondary School

Mumbai

05-2016

Skills

Cadence Virtuoso
Modelsim
Quartus Prime
Verilog
System Verilog
C

TCL
DRC & LVS
Matching
EM / IR
Shielding

Projects

Layout of Auto Zero Comparator circuit
•This circuit is used to compare to different clocks and amplify the difference between two.
•It consisted on multiple stages of differential amplifier and learnt criticality of floorplanning and placement.
Layout of ESD Trigger Circuit
•This protection circuit consists of trigger circuit which includes transistors multiplier in thousands.
•Use of Modgen is necessary in this layout.
Low Power Approximate Multiplier
•Designed the 32-Bit approximate multiplier in Verilog using ModelSim Software which trades of accuracy with speed.

Verification of AHB to APB bridge

•In this project we are to verifying the bridge built between AHB & APB using
different test scenarios.

Timeline