Mohammad Yasin Dudekula

To enhance my professional skills, capabilities, and knowledge within an organization, and to explore opportunities in the VLSI industry. I am eager to engage with industry experts and undertake challenging projects that will stretch the limits of my capabilities.

• System Verilog HVL: Interface and clocking block, OOPs concepts, Constraint randomization, Mailbox and semaphores, Functional coverage, CRCDV and regression testing.
• System Verilog Assertions: Types of assertions, assertion building blocks, sequences with different timing relationships, Implication and Repetition operators.
• UVM: UVM Objects & Components, UVM Factory & overriding methods, Stimulus Modelling, UVM Phases, UVM Configuration, TLM, UVM Sequence, virtual sequence & sequencer.

• Digital Electronics: Combinational & Sequential circuits, FSM, Memories.
• STA: STA Basics, Comparison with DTA, Timing Path and Constraints, Different types of clocks, Clock domain and Variations.
• Verilog Programming: Data types, Operators, Processes, BA & NBA, Delays in Verilog, begin - end & fork join blocks, looping & branching construct, System tasks & Functions, compiler directives, FSM coding.
• Advanced Verilog & Code Coverage: Generate block, Continuous Procedural Assignments, Self-checking testbench, Automatic Tasks, Named Events and Stratified Event Queue, Code Coverage: Statement and branch coverage, Conditional & Expressional Coverage, Toggle & FSM Coverage.

Router 1x3 RTL Design and Verification

HDL : Verilog

HVL : System Verilog

TB Methodology : UVM

EDA Tool : Questa Sim

DESCRIPTION :  The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

• Implemented and Verified RTL using Verilog HDL and UVM.
• Generated functional and code coverage for the RTL verification sign-off.
• Synthesized the design.

AHB2APB Bridge IP Core Verification 

• The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.

Verification of a Dual-Port RAM

• Designed the RAM in Verilog and verified it using Constrained Random Coverage Driven Verification (CRCDV) by developing the TB Architecture in System Verilog

Designing low power Comparator in Cadence

• Schematic design of this Comparator is fabricated in a 0.18micro meter UMC Technology with 1.8V power supply and simulated in Cadence Virtuoso.