Nachiket Acharya

CACHE VERIFICATION & TESTBENCH DEVELOPMENT

• Responsible for end to end verification of the L2/SharedCache which closely interacts with the core and Memcache which interacts with the DRAM.
• Responsible for creating C++ models for the fabric interconnects which played a vital role in cycle based verification of the Caches.
• Involved in all feature verification on the module that involved writing test bench components in SV/UVM , test execution sequences. checkers, coverages.
• Also in the entire process was involved in developing the VIPs which are AMBA CHI5 and AXI 4 from scratch for the verification in UVM and SV.

COHERENCY EXPERTISE

• The project also involved deep understanding of the CHI Coherency protocol in a multi core multi cluster environments. The coherence maintenance was tracked across 2 levels, one at core and one at the L2 cache level.
• Responsible for the complex debugs surrounding Coherency & data integrity in the different levels of testbenches. More than 100 RTL bugs where debugged and reported in this duration.

FEATURE VERIFICATION EXPERTISE

• Support for emulation platforms the testbench code made compatible accordingly involving lot of verilog constructs & C++ checkers for data checking.
• Closely involved with writing power test vectors for power analysis, RTL profiling too. Feature verifications involved some complex RTL features like MMR/CSR configuration, RAS or error logging verification, SRAM hold/Flush verification, ECC and data corruption, scratch pad testing, QOS etc

TOOL DEVELOPMENT

• Developed custom scripts in python to be used by the entire company for regression bucket management.
• Developed ECC injection, corruption and checking tool again used across company sites

TEAM BUILDING

• Guided & built team in the verification process for building and enhancing the test bench components

• Roles as a power design engineer involved 3 main responsibilities

POWER ESTIMATION : An early estimation of all the top interconnects as well as ddr hm for every project.

• This is done by understanding the design changes or updates in every project especially in area, frequency, capacitance and technology node. Calibration of the area delta with respect to technode is taken into account and based on system usecases run on the interconnect for different frequency plans and PVT corner a power budget is proposed for a particular interconnect in the form of releasing a unified power model. This estimation gives a upper hand while calculating the power requirements of the chip at a very early stage. Till date have delivered UPM models for 7 projects.

POWER ANALYSIS : Performing RTL and gate level power analysis using Power Artist and PrimeTime Power tools.

• This involved understanding the power numbers post the rtl activity is fed to the power tools to analyze the annotated list, the flop power, combo power & the clock tree power. Analyzing the clock gating mechanism implemented and architectural implementation involving pipes, clock adapters, root clock gating controllers,raising alarms in case of issues and signing off post review. Have analyzed & signed off 25nocs till date at both rtl and gate level.

POWER OPTIMIZATION : Proposing improvements in power architecture for future projects post analysis of the current projects

• Improving the power collapse features and clock gating mechanism by understanding the data flow and system use case requirements. Optimizing based on mw/MBPS requirements by improving the gating controllers to tap activity based on hysteresis. Was responsible for improving the current project power numbers in the low traffic uses cases by 3.5mW by micro arch change by avoiding data toggle activity based on valid signals
• Roles a NOC design engineer : Involved delivering interconnects for different applications at the DDRSS level. This involves getting the design QBAR clean, CDC clean, PLDRC clean, CLP clean and synth clean

• Worked on re-architecting and re-designing of Trace debug subsystem which tracks the entire system trace data to be monitored and analyzed.
• Currently handling Network On Chip designs for the DDRSS IP interconnect
• Responsible for Power optimization in the NOC but detailed analysis of the Power Intent by development of UPF right at the RTL stage
• Researched in depth about the ARM CTI-CTM networks for wire reduction of trace data via triggers

• Work in R&D department of Qualcomm Interconnect Technology Centre as a senior design verification engineer.
• Have been responsible for verification of various interconnect IPs over past 3 years, which are part of every Qualcomm High tier SOCs.
• Have performed verification of various interconnect units in C++, python & crdl based environment
• Developed verification environment components like Coverage & Monitor for different Qualcomm VIPs in C++

IPs on which end to end verification was done include:

• Serialization Adapter: Performed complete end to end verification of this IP which performs serialization of different payload and header from different Masters
• Axi to Qualcomm Vip converter: Verified this unit which interacts with every AXI Master in Qualcomm SOCs before entering Netowork On Chip(NOC)
• Translation Buffer: Was Fully responsible for verification of this IP, which was Qualcomm’s translation buffer with an internal cache, an replacement to ARM TBU600 & ARM TBU500 IP. Reported around 90 design bugs for this IP over a tenure of 2 years which now into deployment in Qualcomm’s premiers ties & mobile PCs
• Transport to transaction & transaction to packet layer conversion IPs: Verified these IPs which are backbone of Network on chips which handle packet to transaction & vice versa transmission of data & payload from different network interface units.
• Exclusive Monitors: Verified these monitors which handled exclusive transactions from any VIP(AXI, CHI, Qualcomm specific ) with underlying main memory
• Coherency: Have worked extensively in ARM CHI protocol which is responsible for maintaining coherency among various coherent & non coherent IPs. Handled verification of IPs specific to Qualcomm wrapper IP on CHI in analyzing fairness among all these IPs trying to access internal cache.
• Clock domain Crossing: Verified units that are at boundary of 2 clock domains and responsible for maintaining synchronization between them.
• Have also actively verified various other smaller modules which are specific to protocol conversions & coverage closure on all of them

Verification environment development roles involved:

• C++ based coverage module for Qualcomm VIP to collect functional coverages of a Qualcomm specific protocol for service configuration & CSR settings
• CRDL based spy to collect Qualcomm specific Power protocol to tap power monitor
• C++ based traffic generator; a generalized module that can be used for any protocol do generate exclusive transactions (Template based)
• Python based automation of all regression runs, coverage collection & report generation with 0 human efforts & high efficiency
• Ongoing development of make replacement tool for simulation, which handles all rules, dependencies & bsubs to grid smartly by making it faster & smoother

• Learnt System Verilog & UVM as a part of my training program in Seagate Technologies. Accomplished complete understanding of both and start working with 2 live projects just after two months of training
• Responsible for verification of Back End Read DMA, which was a memory controller as a part of thesis work. This was verified entirely in UVM & System verilog
• Undertook APB verification as my MTech final year project submission again done in UVM
• Performed fairly well as a intern and was also offered retention post completion as a full time employee