NAGALAKSHMI KATTA
Hyderabad
Summary
Skilled and detail-oriented Static Timing Analysis (STA) engineer with 3 years of hands-on experience at both block and top levels. Proficient in STA concepts, VLSI fundamentals, and digital design principles. Demonstrated expertise in advanced technology nodes including 16nm, 14nm, and 10nm. Experienced in creating and validating timing ECOs, resolving critical timing violations, and collaborating with cross-functional teams to diagnose and fix timing issues. Adept at analyzing complex timing paths and understanding crosstalk effects. Possess a foundational understanding of OCV/AOCV concepts and basic proficiency in scripting using TCL.
Overview
3
3
years of professional experience
Work History
STA ENGINEER
RENESAS
07.2025 - Current
- Executed timing signoff for post-layout designs using Prime Time.
- Resolved timing violations using constraint adjustments, retiming, and buffer insertion.
- Worked with physical design and cross-functional teams to fix timing/layout issues.
- Automated timing flows for improved process efficiency.
- Documented and presented STA results to internal stakeholders.
STA ENGINEER
RENESAS
12.2024 - 06.2025
- Automated STA tasks to reduce analysis time.
- Applied advanced STA techniques including retiming and multi-cycle path identification.
- Identified and resolved setup/hold and recovery/removal violations.
- Collaborated across design and verification teams to meet timing goals.
STA ENGINEER
SPARKVIZ TECHNOLOGIES PVT LTD
07.2024 - 01.2025
STA ENGINEER
NVIDIA
05.2024 - 12.2024
- Managed timing path constraints across multiple PVT corners.
- Generated and implemented manual ECOs for unfixed violations.
STA ENGINEER
NVIDIA
03.2024 - 12.2024
- Executed top-level STA and generated ECOs using DMSA flow.
- Developed manual ECOs to resolve unfixed paths and closed timing and DRVs.
PROJECT ENGINEER
WIPRO LIMITED COMPANY
05.2022 - 05.2024
- Woking professional with a 2 years of work experience in Wipro technology as Project engineer, with positive attitude to work, seeking a Full-time position and willing to be a part an Information technology team.
Education
B. Tech - ECE
JNTUK
01.2021
Intermediate -
Sri Gowthami Junior College
Darsi01.2017
S.S.C -
MJP AP BC Residential
Markapur01.2015
Skills
- Scripting
- TCL
- Timing ECOs
- Clock Constraints
- Timing Closure
- Setup/Hold/Recovery Violations
Hobbies and Interests
- Listening music
- Watching movies
- Gardening
Job Title
STA Engineer
Timeline
STA ENGINEER
RENESAS
07.2025 - Current
STA ENGINEER
RENESAS
12.2024 - 06.2025
STA ENGINEER
SPARKVIZ TECHNOLOGIES PVT LTD
07.2024 - 01.2025
STA ENGINEER
NVIDIA
05.2024 - 12.2024
STA ENGINEER
NVIDIA
03.2024 - 12.2024
PROJECT ENGINEER
WIPRO LIMITED COMPANY
05.2022 - 05.2024
B. Tech - ECE
JNTUK
Intermediate -
Sri Gowthami Junior College
S.S.C -
MJP AP BC Residential
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