Sumit Kumar Mishra

Synthesis

• Have 2+ years of VLSI Hardware industry experience and worked on Synthesis for 1 high-frequency macro part of MD and 2 partitions part of Mesh network along with QC checks on 3nm technology nodes.
• Hands-on experience with EDA tools used in Synthesis and QCs like Genus, Innovus, Design Compiler, PrimeTime, Conformal, etc.
• Responsible for power, performance, and area analysis and optimization on synthesized netlist in Cadence Innovus tool and met all the design expectations.
• Met the timing expectations of the designs using Retiming, Useful Skew, usage of low VT-cells, etc. And solved congestion issues using addition of soft and partial blockages, cell padding for high-density modules, checking module distribution, and making proper VA bounds.
• Once PPAs are met, perform all the QC checks like ERC, LEC, CLP, ATPG DRC, and Pre-STA to check for timing.

Static Timing Analysis

• Worked on STA for 2 high-frequency partitions, part of a Mesh network, along with DRV fixing using EDA tools like PrimeTime and Tweaker, ensuring closure across various PVT corners. Fixed all kinds of setup, hold, and DRV violations at the block level as well as the interface level for the critical paths using various methods and checked timing impact on PTDMSA for CKECOs.
• Implemented timing optimization techniques, including useful skew, retiming, adjustment of VT group drive strengths of cells, and strategic placement routing adjustments.
• Collaborated with the synthesis and place-and-route teams to optimize the design for performance, power, area, and timing.
• Performed correlation between SOC and block-level timing to analyze and resolve timing gaps.
• Knowledge of concepts of STA (MCMM, AOCV, OCV, CRPR) fixing setup and hold timing violations. Handling RTL linking issues, feedback on SDC to the Design Engineer, RTFF synthesis, DFT insertion according to the scan plan, and analyzing DFT DRC violations. Run, analyze, debug, and fix compression stuck and transition test coverage.
• I had a basic knowledge of HS STA, which helped with timing closure in large designs, with more accurate IO constraints.