NAVEEN KUMAR SINGH

Dynamic R&D Engineer with over 3 years at ITI Limited, specializing in 1G/10G high-speed defense communication systems. Experienced in debugging, protocol encryption, and developing optimized algorithms. Proficient in RTL design using Verilog/VHDL, EDA tools, and hardware debugging, with a focus on data integrity and performance. Seeking roles in RTL and ASIC design to contribute and grow.

• Professional training: Maven Silicon VLSI design and training center, Bangalore
• Advanced VLSI Design and System Verilog (2022-23)
• MSUID: MS/21-22/2473
• Udemy certifications (Instructor: Kumar Khandagle)
• Verilog
• SystemVerilog part 1
• SystemVerilog part 2
• Verification series part 3: UVM essentials

• AMBA AXI4-Lite & APB protocol verification – UVM testbenches: gained hands-on experience developing SystemVerilog UVM testbenches for AXI4-Lite and AMBA APB protocols, designed reusable components (driver, monitor, agent, scoreboard), supported parallel read/write (AXI4-Lite), and integrated Synopsys VIPs, implemented functional coverage and SystemVerilog assertions (SVA) for protocol validation and timing checks, ensured reset synchronization, followed structured UVM phase methodology, and used Synopsys VCS and Verdi for simulation and debugging, achieving 100% functional coverage
• Router 1x3 – TCP/IP RTL design: Designed Verilog RTL for a TCP/IP-based 1x3 router with FIFO, synchronizer, and FSM, ensuring proper reset and CDC handling, verified using SystemVerilog UVM testbench and SVA, simulated with VCS, debugged in Verdi, achieved 92.3% code coverage, and 100% functional coverage

• Received commendation by the unit head for displaying utmost dedication, commitment, and professional competence (2024)
• Gate qualified 2019 (rank: 3207)