NAVEEN KUMAR SINGH
Bangalore
Summary
Dynamic R&D Engineer with over 3 years at ITI Limited, specializing in 1G/10G high-speed defense communication systems. Experienced in debugging, protocol encryption, and developing optimized algorithms. Proficient in RTL design using Verilog/VHDL, EDA tools, and hardware debugging, with a focus on data integrity and performance. Seeking roles in RTL and ASIC design to contribute and grow.
Overview
3
3
years of professional experience
1
1
Certification
Work History
ASSISTANT EXECUTIVE ENGINEER | R&D Department
ITI Limited
Bangalore
07.2022 - Current
- Resolved protocol encryption issues in 1G/10G Ethernet FPGA design, ensuring DRDO-SAG compliance.
- Debugged hanging and buffer overflow issues to ensure stable, secure data flow in defense secrecy devices.
- Designed and integrated microarchitecture/sub-modules for security features, like padding validation and checksum logic.
- Implemented packet drop/pass mechanisms to enhance network security.
- Verified functionality using ModelSim, a custom VHDL testbench, and SystemVerilog Assertions (SVA).
- Synthesized design on Kintex-7 FPGA (160T) using Xilinx ISE 14.7.
- Used ChipScope Pro, network/protocol analyzers, for signal tracing and validation.
- Conducted real-time hardware testing and on-site validation at customer premises.
- Developed proprietary, secure communication algorithms for the Indian Army, NSG, ITBP, and MHA agencies.
- Implemented algorithm microarchitectures on the Artix-6 FPGA.
- Validated using Wireshark, Ostinato, and Ethernet traffic generators.
- Secured multi-channel IP, analog, video, and file transfers.
- Successfully completed firmware testing, debugging, and field trials in live defense environments.
Education
Master of Technology (MTech) - Power Electronics and Drives (PED)
MNNIT Allahabad
Uttar Pradesh, India08-2021
Bachelor of Technology (BTech) - Electrical Engineering (EE)
AKTU
Prayagraj, Uttar Pradesh, India06-2017
Skills
- Hardware description languages: VHDL, Verilog
- Verification language: SystemVerilog
- Verification methodology: UVM
- communication protocols: AMBA APB, AXI4-Lite, I2C, UART
- EDA tools: ModelSim, Xilinx ISE, Vivado, VCS, Synopsys Verdi/DVE
- Debugging tools: Xilinx JTAG, traffic analyzer, Chipscope
- Programming languages: Perl, Basic Python
Certification
- Professional training: Maven Silicon VLSI design and training center, Bangalore
- Advanced VLSI Design and System Verilog (2022-23)
- MSUID: MS/21-22/2473
- Udemy certifications (Instructor: Kumar Khandagle)
- Verilog
- SystemVerilog part 1
- SystemVerilog part 2
- Verification series part 3: UVM essentials
Training Projects
- AMBA AXI4-Lite & APB protocol verification – UVM testbenches: gained hands-on experience developing SystemVerilog UVM testbenches for AXI4-Lite and AMBA APB protocols, designed reusable components (driver, monitor, agent, scoreboard), supported parallel read/write (AXI4-Lite), and integrated Synopsys VIPs, implemented functional coverage and SystemVerilog assertions (SVA) for protocol validation and timing checks, ensured reset synchronization, followed structured UVM phase methodology, and used Synopsys VCS and Verdi for simulation and debugging, achieving 100% functional coverage
- Router 1x3 – TCP/IP RTL design: Designed Verilog RTL for a TCP/IP-based 1x3 router with FIFO, synchronizer, and FSM, ensuring proper reset and CDC handling, verified using SystemVerilog UVM testbench and SVA, simulated with VCS, debugged in Verdi, achieved 92.3% code coverage, and 100% functional coverage
Accomplishments
- Received commendation by the unit head for displaying utmost dedication, commitment, and professional competence (2024)
- Gate qualified 2019 (rank: 3207)
Timeline
ASSISTANT EXECUTIVE ENGINEER | R&D Department
ITI Limited
07.2022 - Current
Master of Technology (MTech) - Power Electronics and Drives (PED)
MNNIT Allahabad
Bachelor of Technology (BTech) - Electrical Engineering (EE)
AKTU
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