Shreya Singh

Seeking professional and personal growth in a position utilizing extensive VLSI Design experience. Worked as both an ASIC design engineer and IP design engineer in mobile and automotive SoCs. Have had the opportunity to learn and contribute in the domains of cpu subsystem, system level non coherent caches in mobile SoCs and safety, system level reset , power controller, MIPI CSI2 based high speed serial link for automotive SoCs.

• System and Method For Coherent Channel Enable/Disable on a MIPI CSI2 Subsystem, Stephan Matthias Herrmann, Gaurav Gupta, Naveen Kumar Jain, Shreya Singh
• System and Method of Embedded Data Capture in a single buffer on a MIPI CSI2 link, Stephan Matthias Herrmann, Naveen Kumar Jain, Shreya Singh, Shivali Jain
• Real-time ON-CHIP Data Transfer System, Naveen Kumar Jain, Joachim Fader, Shreya Singh, Nishant Jain, Anshul Goel
• System and Method of Configuring an External Radar Device Through High Speed Reverse Data Transmission, Maik Brett, Naveen Kumar Jain, Shreya Singh
• Fast link turnaround using MIPI D-PHY, Maik Brett, Naveen Kumar Jain, Shreya Singh
• System and method for continuous operation of vision/radar systems in presence of bit errors, Pavel Bohacik, Shreya Singh, Nishant Jain, Anshul Goel, Shivali Jain, Naveen Kumar Jain
• System and method of early turnaround indication for a D-PHY communication interface, Maik Brett, Naveen Kumar Jain, Shreya Singh, Anshul Goel
• System and method for managing testing and availability of critical components on system-on-chip, Neha Srivastava, Shreya Singh

• Krishna Thakur, Biswaprakash Navajeevan, Deependra Jain, Shreya Singh, Avinash Chandra Tripathi "An Integrated approach to achieve reduced relock-time for a fixed operating point of Analog PLL" awarded defensive publication and published on ip.com
• Krishna Thakur, Deependra Jain, Shreya Singh, Ian Caldwell, Gordon Campbell, "PLL BIST for test time saving and enhancement of safety critical applications", awarded innovation award
• Mayank Parasrampuria, Anurag Jindal, Dirk Wendel, Shreya Singh,"Adaptive MBIST Sequencer", awarded innovation award

• Recognition for Safety IP development (part of a team of 7 people)
• Second highest innovator in 2019 (NXP India) for patent pursues
• Top innovator award in 2018 for maximum patent pursues in NXP India
• Awarded "Team Bravo" for Memory BIST Implementation on C28 device first time right execution. (2015)
• Received 3 "Winning Starts Here" for extra-ordinary performance and ownership in Digital PLL, STCU, MIPI and safety IPs. (2012, 2017, 2021)
• Awarded 3 "Cheer for Peer" award from cross-functional colleagues for outstanding support and cooperation (Freescale). (2012, 2013, 2015)

• Krishna Thakur, Biswaprakash Navajeevan, Deependra Jain, Shreya Singh, Avinash Chandra Tripathi "An Integrated approach to achieve reduced relock-time for a fixed operating point of Analog PLL" awarded defensive publication and published on ip.com
• Sunil Deep maheshwari, Prashant Bhargava & Shreya Singh "PLL Subsystem architectures for SoC design", EDN
• Shreya Singh, Abhinav Gaur, Amit Pal,"Adding CRC to Bist improves Soc safety and reliability", EDN

Won the best team award in women’s category in Freescale Level table tennis competition. (2014), Won bronze medal in table tennis women’s category in Corporate Challenge at Noida (2013)