Shreya Singh
Bengaluru
Summary
Seeking professional and personal growth in a position utilizing extensive VLSI Design experience. Worked as both an ASIC design engineer and IP design engineer in mobile and automotive SoCs. Have had the opportunity to learn and contribute in the domains of cpu subsystem, system level non coherent caches in mobile SoCs and safety, system level reset , power controller, MIPI CSI2 based high speed serial link for automotive SoCs.
Overview
13
13
years of professional experience
Work History
ASIC Design Engineer
Google India
2023.01 - Current
- Worked on delivery of front end constraints for the CPU subsystem for mobile platform
- Collaborated with physical design teams to verify constraints, achieve timing closure and optimize place and route.
- Also worked as a design lead for system level non coherent cache system for mobile platforms.
Principal Design Engineer
NXP Semiconductor
2022.04
- Became a notable inventor with 10 patent grants in July,2022
- Worked on a coherent cache multicore accelerator IP for timing closure and tools closure
- Was the debug subsystem integration lead for the block.
Staff Design Engineer
NXP Semiconductor
2018.04 - 2022.03
- Worked on an architectural design for a tool to select between SoC and SiP solutions in an edge processing automotive chip solution
- Currently involved in architectural specification discussions and design of safety fault collection and control unit for an automotive architecture offering virtualization principles.
Senior Design Engineer
NXP Semiconductor
2014.02 - 2018.03
- Was involved in architectural specification discussions and design of MIPICSI2 +MIPI DPHY interface for automotive applications in the vision and radar domains as the link of choice for high speed sensor data reception and transmission
- Was involved in finalizing the specification requirement of the new design for radar and vision data reception for automotive links using MIPICSI2 protocol and vision data transmission using MIPICSI2 link.
Design Engineer
2011.06 - 2014.01
- Owned assorted IPs including digital wrapper around analog PLL, safety relevant modules for LBIST, MBIST sequencing, memory error management unit, System level modules – pin muxing control module, MIPICSI2 for infotainment chip
- Owned all the stated IPs, developed understanding of these blocks.
Education
B.E. (Hons.) -
Birla Institute of Technology, Mesra, India
Class XII, CBSE -
DAV Shyamli, Ranchi, India
Class X, ICSE -
Loreto Convent, Ranchi, India
Skills
- Spyglass, RTL Compiler, Design Compiler, ATPG, CDC, Lint, SimVision, IMC, Verdi, DVE, Questa, Timevision, Genus
- Verilog, VHDL, C, System Verilog, SVP
- Constraint development
- IP Integration
- Low Power Design Techniques
- Analog mixed-signal design
- Scripting Languages
- Timing closure
- RTL design proficiency
- Hardware description languages
- Digital Circuit Design
- Simulations
Patents
- System and Method For Coherent Channel Enable/Disable on a MIPI CSI2 Subsystem, Stephan Matthias Herrmann, Gaurav Gupta, Naveen Kumar Jain, Shreya Singh
- System and Method of Embedded Data Capture in a single buffer on a MIPI CSI2 link, Stephan Matthias Herrmann, Naveen Kumar Jain, Shreya Singh, Shivali Jain
- Real-time ON-CHIP Data Transfer System, Naveen Kumar Jain, Joachim Fader, Shreya Singh, Nishant Jain, Anshul Goel
- System and Method of Configuring an External Radar Device Through High Speed Reverse Data Transmission, Maik Brett, Naveen Kumar Jain, Shreya Singh
- Fast link turnaround using MIPI D-PHY, Maik Brett, Naveen Kumar Jain, Shreya Singh
- System and method for continuous operation of vision/radar systems in presence of bit errors, Pavel Bohacik, Shreya Singh, Nishant Jain, Anshul Goel, Shivali Jain, Naveen Kumar Jain
- System and method of early turnaround indication for a D-PHY communication interface, Maik Brett, Naveen Kumar Jain, Shreya Singh, Anshul Goel
- System and method for managing testing and availability of critical components on system-on-chip, Neha Srivastava, Shreya Singh
Other Disclosure Awards
- Krishna Thakur, Biswaprakash Navajeevan, Deependra Jain, Shreya Singh, Avinash Chandra Tripathi "An Integrated approach to achieve reduced relock-time for a fixed operating point of Analog PLL" awarded defensive publication and published on ip.com
- Krishna Thakur, Deependra Jain, Shreya Singh, Ian Caldwell, Gordon Campbell, "PLL BIST for test time saving and enhancement of safety critical applications", awarded innovation award
- Mayank Parasrampuria, Anurag Jindal, Dirk Wendel, Shreya Singh,"Adaptive MBIST Sequencer", awarded innovation award
Awards
- Recognition for Safety IP development (part of a team of 7 people)
- Second highest innovator in 2019 (NXP India) for patent pursues
- Top innovator award in 2018 for maximum patent pursues in NXP India
- Awarded "Team Bravo" for Memory BIST Implementation on C28 device first time right execution. (2015)
- Received 3 "Winning Starts Here" for extra-ordinary performance and ownership in Digital PLL, STCU, MIPI and safety IPs. (2012, 2017, 2021)
- Awarded 3 "Cheer for Peer" award from cross-functional colleagues for outstanding support and cooperation (Freescale). (2012, 2013, 2015)
Positions And Responsibilities
SPOC, Design for Test, Freescale Semiconductor, Noida, India, 03/2015, Present, Actively driving DFT goal in the Digital IP team., Evaluated Synopsys SPYGLASS tool’s new features for RTL DFT and worked on its deployment., Coached global Digital IP team to get accustomed with the new DFT flow., Represented IP team for safety portfolio in global discussions (2015-2017).
Publications
- Krishna Thakur, Biswaprakash Navajeevan, Deependra Jain, Shreya Singh, Avinash Chandra Tripathi "An Integrated approach to achieve reduced relock-time for a fixed operating point of Analog PLL" awarded defensive publication and published on ip.com
- Sunil Deep maheshwari, Prashant Bhargava & Shreya Singh "PLL Subsystem architectures for SoC design", EDN
- Shreya Singh, Abhinav Gaur, Amit Pal,"Adding CRC to Bist improves Soc safety and reliability", EDN
Extracurricular Activities
Won the best team award in women’s category in Freescale Level table tennis competition. (2014), Won bronze medal in table tennis women’s category in Corporate Challenge at Noida (2013)
Timeline
ASIC Design Engineer
Google India
2023.01 - Current
Principal Design Engineer
NXP Semiconductor
2022.04
Staff Design Engineer
NXP Semiconductor
2018.04 - 2022.03
Senior Design Engineer
NXP Semiconductor
2014.02 - 2018.03
Design Engineer
2011.06 - 2014.01
B.E. (Hons.) -
Birla Institute of Technology, Mesra, India
Class XII, CBSE -
DAV Shyamli, Ranchi, India
Class X, ICSE -
Loreto Convent, Ranchi, India
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