Summary
Overview
Work History
Education
Skills
LANGUAGES
HOBBIES & INTEREST
OTHER CONTRIBUTIONS
MAJOR PROJECTS
Timeline
Generic
NIKHIL K

NIKHIL K

Bangalore

Summary

Skilled in designing IC layout dimensions with knowledge of IC layout design methods and techniques with over 10+years of experience. Strengths in Cadence virtuoso tool to make efficient layout Design. Looking for an opportunity to work as an IC layout engineer in a renowned organization.

Overview

3
3
years of professional experience

Work History

Lead Design Engineer

Cadence Design Systems Ind Pvt Ltd
01.2022 - Current
  • I have total 10+ years of experience in Analog layout, Part of Cadence Design Systems Ind Pvt Ltd from 2013 to 2025 including internship.
  • Lead Design Engineer 2022 - 2025
  • Design Engineer II 2019 - 2022
  • Design Engineer I 2016 - 2019
  • Associate Design Engineer 2014 - 2016
  • Internship 2013 - 2014

Education

B tech - Engineering Technology

BITS Pilani
01-2024

Diploma - Electronic Engineering

GPTC Kannur
01-2012

Higher Secondary Education -

GVHSS Madappally
01-2009

SSLC -

GVHSS Madappally
01-2007

Skills

  • Good understanding of advanced semiconductor technology process
  • Experience in custom layout designing of lower node technology – TSMC (2nm,3nm,5nm,7nm,16nm &28nm) Samsung (4nm,7nm, & 14nm) GF (12nm) Intel (i14)
  • Expertize in High-speed complex layout Designs
  • Good knowledge in Cadence virtuoso layout editor,PVS/Pegasus verification tool
  • Good knowledge of Managing reliability issues like EMIR, Antenna Effect,Latch-up,ESD Protection etc

LANGUAGES

English
Malayalam
Hindi

HOBBIES & INTEREST

. Playing Cricket,Football & Badminton

. Listening Music

. Watching Movies

OTHER CONTRIBUTIONS

Served as Mentor for the Juniors Engineers, Trained them during the Internship. Served as an active member of Campus recruitment drive for the Analog layout team for multiple years.

MAJOR PROJECTS

GDDR (TSMC 3NM)


Worked closely with the Design team for the smooth execution of project . Handled the critical sub blocks and reduced the BA iterations.

Timeline

Lead Design Engineer

Cadence Design Systems Ind Pvt Ltd
01.2022 - Current

B tech - Engineering Technology

BITS Pilani

Diploma - Electronic Engineering

GPTC Kannur

Higher Secondary Education -

GVHSS Madappally

SSLC -

GVHSS Madappally
NIKHIL K