Summary
Overview
Work History
Education
Skills
Websites
Timeline
Generic

NITISH KUMAR

Bengaluru

Summary

Experienced GPU Logic Design Engineer with 3+ years of experience as GPU RTL integration engineer and 1 year internship experience with CPU PD backend team, Proven expertise in integrating complex IP blocks, managing RTL-level issues, and ensuring successful synthesis and STA handoff.

Overview

4
4
years of professional experience

Work History

GPU Logic Design Engineer

Intel
Bengaluru
06.2022 - Current
  • Working with the GPU integration/verification team for the next generation of graphics, responsibilities include the integration of sub-IPs to form the Graphics IP and performing the integration of functional units. Bring up the model functionally, with a good understanding of the Configuration/BOOT flow.
  • Develop and verify GPU IP to deliver high-quality models. Design, verification, and integration methodology development. Run, analyze, and fix various quality check tools and flows, such as connectivity checks at the standard interface level and IP boundaries level, dangles cleanup in RTL modules using full chip activity and checker tool, CDC, RDC, define power domains using UPF, and hit performance, power, and area targets, and low power checks using VCLP.
  • Works with cross-functional teams to ensure designs are delivered on time, and with the highest quality, by incorporating proper checks at every stage of the design process. I also have expertise in industry-standard tools such as Synopsys VCS, Verdi, Conformal, and DC.

Graduate Technical Intern

Intel
Bengaluru
06.2021 - 05.2022
  • Works with backend engineers on pre and post physical design timing closure with a strong background in static timing analysis, physical verification, noise, quality, power closure in functional unit block.

Education

M.Tech - VLSI Design

National Institute of Technology
Jalandhar
07.2022

Skills

  • GPU logic design Integration
  • RTL Design
  • Static timing analysis
  • Synopsys VCS
  • VC CDC/RDC ,LINT
  • Conformal check

Timeline

GPU Logic Design Engineer

Intel
06.2022 - Current

Graduate Technical Intern

Intel
06.2021 - 05.2022

M.Tech - VLSI Design

National Institute of Technology
NITISH KUMAR