Parimita Bai
Bangalore
Summary
Experienced Processor Verification Engineer with over 5 years of experience in ARM and X86 based processor verification using FPGA and simulation environments. Skilled in debugging fails and running regression .Seeking a full-time position to leverage skills and contribute effectively to the team and organization's success.
Overview
6
6
years of professional experience
Work History
Senior Verification Engineer
Mirafra Technology Private Limited
01.2022 - Current
- Understanding ARM architecture
- Verifying full system on FPGA using randomized test generated by GENASM tool .
- Planning verification staging and running regression according to the plan.
- Debugging RTL fail on waveform and debugging test issues.
- Analyzing various parameter and improving stimulus to improve overall regression efficiency .
- Worked on power coverage and its analysis.
- Developing Python scripts as needed as part of stimulus improvement plan.
Senior Verification Engineer
VerifIQ Technologies
02.2021 - 12.2021
- Worked on AMD X86-based processor verification on simulation
- Running regression on weekly basis.
- Debugged directed test cases written in assembly-based language and fixed them on need basis.
- Debugging RTL fails using verdi.
- Created line and toggle coverage reports.
- Check-in source files frequently using Perforce command.
- Worked on different feature like HDT and DSM.
Verification Engineer
Black Pepper Technology
07.2018 - 01.2021
- Developed verification IP for I2C protocol using SV.
- Developed verification IP for AHB protocol sing UVM.
Client project at AMD
- Worked on AMD X86-based processor verification
- Completed a training program on modern 64-bit computer architecture
- Running regression on weekly basis.
- Debugging directed test case fails and File them on JIRA.
- Check-in source file on need basis using Perforce command.
Education
M.Tech in VLSI and Embedded System Design -
Biju Pattnaik Institute of Technology
Rourkela,Odisha08.2017
Skills
- Having 5 years of experience as verification engineer
- Experienced in debugging both RTL and test fail
- Fair understanding in modern computer architecture
- Adequate understanding of OOPS concept
- Hands on experience on System Verilog and UVM
- Experienced in GVIM and Linux command
- Worked on FPGA based verification and simulation based verification
- Computer architecture - ARM, X86
- Programming language - Verilog, SV,C, Python, Assembly language
- Protocol- AMBA AXI,AHB,I2C
Personal Information
Date of Birth: 12/23/91
Training
- 6-month Frontend Verification at VLSI GURU, including Verilog, System Verilog, UVM, and protocols (APB, AXI, AHB).
- Verification IP development for AXI protocol and AHB protocol using System Verilog, UVM, and tools like Verdi and Questasim.
Timeline
Senior Verification Engineer
Mirafra Technology Private Limited
01.2022 - Current
Senior Verification Engineer
VerifIQ Technologies
02.2021 - 12.2021
Verification Engineer
Black Pepper Technology
07.2018 - 01.2021
M.Tech in VLSI and Embedded System Design -
Biju Pattnaik Institute of Technology
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